14:50

Temperature, Statistics fine (see screenshots).

System wide checks fine (see below).

All FEEs pass clock check.

All FEEs pass White Rabbit check.

ADC Calibration check:

FEE64 module aida02 failed
FEE64 module aida16 failed
Calibration test result: Passed 14, Failed 2

If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module

FPGA timestamp error check:

         Base         Current         Difference
aida09 fault      0x1 :      0xa :      9  
FPGA Timestamp error counter test result: Passed 15, Failed 1
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last

16:00 Slow comp thresh lowered to 100 keV in preparation for detector moving. Will have to test systematically what is the highest threshold we can accept

17:00 Temps fine. No overnight run.