16:30
All System checks okay, except for:
FPGA Timestamp error:
Base Current Difference
aida12 fault 0x0 : 0x1b : 27
FPGA Timestamp error counter test result: Passed 11, Failed 1
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
Temperature Checks: See attachment 1
Statistics Checks: See attachment 2
Bias & Leakage Currents: See attachment 3
18:09
All system checks okay, except for:
FPGA Timestamp error:
Base Current Difference
aida12 fault 0x0 : 0x1d : 29
FPGA Timestamp error counter test result: Passed 11, Failed 1
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
Temperature checks: See attachment 4
Statistics Checks: See attachment 5
Bias & Leakage Currents: See attachment 6
19:40
All system checks okay, except for:
FPGA Timestamp error:
Base Current Difference
aida12 fault 0x0 : 0x1d : 29
FPGA Timestamp error counter test result: Passed 11, Failed 1
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
Temperature checks: See attachment 7
Statistics Checks: See attachment 8
Bias & Leakage Currents: See attachment 9
*Beam being tuned to another experiment (R3B) - all DSSD implants fluctuating back and forth to 0 Hz for around the last hour or so*
22:30
General check
Rates, Voltages, Temperatures, Ucesb are attached 10,11,12,13
Its been noticed that aida04 temp. is incresing to about 65 (red), still below 70.
the system wide check are all ok except FPGA
Base Current Difference
aida12 fault 0x0 : 0x1d : 29
FPGA Timestamp error counter test result: Passed 11, Failed 1
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
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