 Wed Jun 22 10:09:12 2022, PJCS, INFO: FEE64 supply Voltages
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Study of the FEE64 power supply distribution has yielded the following :-
The most sensitive regulator, as regards the device voltage input, is the TPS51100 that supplies the DDR memory reference voltages. This
requires +4.75 to +5.25 volts. This is supplied from the Power input connector +5v input. |
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Wed Sep 14 19:07:07 2022, PJCS, INFO : Three Merger Statistics explained
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There are three Merger statistics that can be used to better understand how the data flow through the Merger system is proceeding.
Two are from the Link task and one is from the Merger.They are all "No data buffers avaliable" with #1, #2, #3 at the end.
#1: This is incremented when the Link task has a data item to put in the queue for the Merge process but there is no room. |
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Fri May 7 19:47:54 2021, PJCS, HowTo mitigate excessive temperature in an FEE64
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After tests in the Daresbury T9 system.
Disabling the waveform ADCs in an FEE64 which is running with the FPGA over temperature will drop the FPGA temperature by 10 degrees.
To disable the ADCs open the Local Control browser window and set the ADC Control register , @2, to 0xFF |
Mon May 20 13:51:45 2019, NH, HowTo Verify WR Times 
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The latest version of MIDAS has a new page to check the WR timestamp of each FEE.
In AIDA Hardware control click: GSI White Rabbit Control
In expert options click: Collect all Timestamps |
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Wed Mar 31 15:46:09 2021, PJCS, HowTo : Synchronize the ASIC clocks.
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To Synchronize the FEE64 ASIC clocks to rise at the same timestamp time use the System function Synchronise the ASIC clocks in the System
Wide Checks browser page.
The Server will read the current timestamp value and calculate, based on the number of FEEs and the access delay, a timestamp value sometime |
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Wed Mar 31 12:46:10 2021, PJCS, HowTo : Calibrate the LMK3200 clock devices
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Here is a document showing how and where to calibrate the LMK3200 devices that lock to the system clock and generate the clocks for the ADCs and the
FPGA internal logic. |
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Tue Mar 26 14:58:09 2019, NH, VP, How to reset merger
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If the merger doesn't show "xfer Links => Merger" at the top, it is probably the merger setting has been corrupted somehow. This is
how to reset it
If you go to the web page from which you started the Merge and TapeServer |
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Wed Aug 14 14:40:18 2019, NH, High Frequency Noise in AIDA
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Figures of intense high frequency noise pickup in AIDA.
Will investigate source in S4.
Edit: Period is approx 40 cycles / approx 2.5 MHz (?) |
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Tue Feb 25 09:55:59 2020, NH, HV Scope Traces 10x
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Looking at the HV bias in a scope to see if it is the source of noise especially on the p+n side
Channel 1: HV Core channel 4
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Wed Dec 4 09:57:24 2024, TD, HISPEC DESPEC meeting presentation - November 2024 -0 Summary of AIDA performance 2024
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Sat Mar 5 10:43:45 2022, OH, NH, Grounding and noise tests 4th-5th March Summary 13x
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Tests performed
After leaving overnight noticed the pulser was not fully inserted into aida09
Little change in rates
observed in 9 but otherwise nothing else
Connected bias of aida02 (n+n ground) to aida06 (n+n ground) and likewise 4-8
No
change observed in rates
Also tested covering the snout in light tight material
No Changes
Unplugged |
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Fri Oct 29 23:00:04 2021, NH, Ground cable information
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For future refinement of the AIDA ground cables using copper bus bar or similar:
Thin cable (from AIDA FEEs to common connection point)
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Tue Oct 28 12:43:38 2025, JB, GB, MP, AM, Further setup of tests for 207Bi test 14x
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- Ch 2 and 3 of CAEN HV module changed to negative polarity, Ch 0,1 still with positive polarity
- Bias changed from the n+n to the p+n side (now Ch 2,3) - att. 1
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Wed Oct 29 08:12:35 2025, MP, Further setup for 207Bi test
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Inspection of side FEEs (2,6,4,8) and possible grounding improvements:
- all screws and nuts for copper connections were tightenedFee
- FEE 6 was isolated from the copper connection grounding FEE2 with insulating tape (attachment 1) |
 Wed Oct 29 12:56:29 2025, TD, Further setup for 207Bi test
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Remember that 'ADC calibration' refers to the setup of the fast serial output of the AD9222 Octal, 50MSPS, 14 bit ADC which generates the waveforms
- if the FEE64 is unable to calibrate all that happens is that you will not be able to see preamp output waveforms. Energy spectra will work regardless
as they use a different ADC. |
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Thu Mar 4 11:16:13 2021, OH, Further cases of possible database issues
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During testing for the S452 experiment yesterday we were running through the steps of a restart.
The FEEs were not powercycled at this stage but the MIDAS server was restarted.
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Fri Apr 8 08:59:42 2022, OH, NH, Friday 8th April 11x
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09:59 Noticed that the right hand ribbon cable for aida07 was offset vertically by 1. i.e. Only 1 of the 2 rows of pins in. Unbiassed detectors and reconnected.
Rebiassed detectors - leakage current on DSSD2 increased to 9.96uA - Attachment 1
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Fri Mar 8 16:05:57 2024, JB, CC, TD, NH, Friday 8 March
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Bias tests of AIDA on individual wafers and in parallel. Spreadsheet can be found in attachment 1, and graphic results can be seen in Attachment 2. Summary:
Upstream detector cannot be biased in parallel nor individually. Downstream detector can be biased with positively and each wafer can individually be biased
negatively. In parallel, it was not possible to bias the downstream detector negatively as indicated by the tests below. |
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Fri May 7 13:11:22 2021, NH, Friday 7th May
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14:11 - Alpha has been running most of morning
Just saw rates in tape spike to 6 MB/s...
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Fri Jun 7 16:08:37 2024, TD, Friday 7 June 19x
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05.01 DSSSD bias & leakage current - attachment 1
FEE64 temperatures OK - attachment 2
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