| ID |
Date |
Author |
Subject |
Text |
 |
|
178
|
Mon Mar 14 11:27:47 2016 |
PJCS | ASIC_clock synchronisation across the system | During 'SETUP' the ASIC readout clock (
500KHz ) is synchronised to the SYNC pulse
in V8.10 and later versions of the VHDL. |
|
|
177
|
Fri Mar 11 15:31:53 2016 |
TD | Analysis of R34_0 | lancre> ./analyser R34_0
*** GREAT format 3.2.0 analyser - TD - May
2014
|
|
|
176
|
Thu Mar 10 16:35:39 2016 |
TD : PJCS | Report - high - AIDA timestamps | > Version 8 firmware
>
> Analysing R37_* data files (see https://elog.ph.ed.ac.uk/AIDA/160)
|
|
|
175
|
Wed Mar 9 17:31:58 2016 |
TD | Report - high - LEC/MEC fast comparator issues | >
> Fast comparator rate spectra and statistics
do not appear to working as expected. See |
|
|
174
|
Wed Mar 9 16:18:01 2016 |
TD | nndhcp021 AIDA server Httpd/TapeServer/Merger startup | Starting Httpd for the TapeServer/Merger,
TapeServer and Merger for AIDA produces
three terminal windows which will display |
|
|
173
|
Wed Mar 9 12:16:01 2016 |
TD | Wednesday 9 March | MSL type BB18(DS)-1000 serial 2998-22
Bias +200V, I_L +=6.505uA, ambient temperature
+19.8 deg C
|
|
|
172
|
Tue Mar 8 16:29:07 2016 |
TD | Report - high - AIDA timestamps | Version 8 firmware
Analysing R37_* data files (see https://elog.ph.ed.ac.uk/AIDA/160)
|
|
|
171
|
Tue Mar 8 15:40:57 2016 |
TD | Tuesday 8 March | MSL type BB18(DS)-1000 serial 2998-22
Bias +200V, I_L +=6.705uA, ambient temperature
+19.8 deg C
|
|
|
170
|
Tue Mar 8 15:32:53 2016 |
TD | Report - low - run control frame issue with multiple streams | The run control frame does not appear to update
the data transfer 'X' tag
for all FEE modules after selecting 'Enable |
|
|
169
|
Tue Mar 8 15:09:49 2016 |
TD | Report - high - LEC/MEC fast comparator issues |
Fast comparator rate spectra and statistics
do not appear to working as expected. See |
6x |
|
168
|
Tue Mar 8 12:11:56 2016 |
CG, AE | RIKEN maintenance progress |
|
|
|
167
|
Tue Mar 8 06:00:45 2016 |
CG, AE | RIKEN maintenance progress | 07/03/16
The new snout doesn't fit due to
the screw holes being misaligned. I am going |
|
|
166
|
Wed Mar 2 11:59:48 2016 |
PJCS | First data with two streams merged from one FEE64 | The Fail bit is used to indicate The Timing
Vernier word.
I'll post a seperate Elog entry to explain |
|
|
165
|
Thu Feb 25 12:47:43 2016 |
PJCS | First data with two streams merged from one FEE64 |
My GREAT data analyser program reports that
the 'fail' bit is set ?
|
|
|
164
|
Wed Feb 24 16:13:24 2016 |
PJCS | First data with two streams merged from one FEE64 |
|
|
|
163
|
Wed Feb 24 15:46:11 2016 |
PJCS | OR64 - OR of all the ASIC discriminator channels after application of a mask | Firmware version8 number 8 has an OR64
added which can be routed, using the Local
control, to the Trigger output and hence |
|
|
162
|
Wed Feb 24 14:53:41 2016 |
PJCS | First data with two streams merged from one FEE64 | nnaida2 running Version 8 Firmware and
data acquisition software outputting both
and ASIC data stream and a Waveform data |
|
|
161
|
Wed Feb 24 13:54:53 2016 |
TD | Report - low - FEE temperature plot displays incorrect dates |
See Attachment 1
|
|
|
160
|
Wed Feb 24 10:25:35 2016 |
TD | Wednesday 24 February 2016 | MSL type BB18(DS)-1000 serial 2998-22
Bias +200V, I_L +=5.770uA, ambient temperature
+19.8 deg C
|
|
|
159
|
Tue Feb 23 12:16:08 2016 |
TD | Tuesday 23 February 2016 | MSL type BB18(DS)-1000 serial 2998-22
Bias +200V, I_L +=5.570uA, ambient temperature
+19.8 deg C
|
|