Mon May 4 01:23:48 2015, TD, Unable to obtain Data Acqusition Statistics frame
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Got the error Server Internal Error
while trying to obtain /DataAcquisitionControl/DataAcquisitionStats.tml.
can't read "cgiNUMdata": no such variable while executing "InsertLog "cgidata= ([llength $cgidata]) $cgiNUMdata"" |
Mon May 4 02:03:24 2015, TD, Unable to obtain Data Acqusition Statistics frame
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Quote:
Got the error Server Internal Error |
Mon May 4 01:27:56 2015, JA, TD, AE, CG & JLT, Monday 4 May 2015 16x
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09.18 SN changed degrader to 5.7mm Al (4mm + all variable degraders + additional 1mm)
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Sun May 3 01:32:18 2015, JA, TD, AE, CG, VP & JLT, Sunday 3 May 2015
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09.19 Beam off on arrival, now back
R51 running
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Sat May 2 19:20:59 2015, AE, run R51 online spectra    
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Online spectra to monitor condition during run R51.
Position and energy spectra indicate implantation in 2nd DSSD.
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Sat May 2 19:17:25 2015, AE, time-stamp for event reconstruction    
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Some first analysis of building events to look for implants and decays
Using both DISC and slow comparator values for time-stamp (whatever is available). Clearly there are some ADC
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Sat May 2 14:41:20 2015, JA, TD, AE, CG, VP & JLT, MUSIC detector signals 
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Adjusted setting of MUSIC detector signals during break
MUSIC ---> (16dB att) --> Lemo split ---> J13 |
Sat May 2 02:04:50 2015, JA, TD, AE, CG, VP & JLT, Saturday 2 May 2015 50x
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0055: Degrader changed. 1mm removed.
1.4mm total
0537: R38 ends nnaida11 slow comparator 0x20 -> 0x40 LEC fast comparator -> 0xff |
Thu Apr 30 15:28:25 2015, Patrick Coleman-Smith, High Energy Spectra from LYCCA with pulser
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I have an eight FEE64 system now in place on the LYCCA chamber with a PB-5 pulser going into the adapter cards test input. The test capacitor is 30pF.
I was going to explore the effect of the thresholds on the pulser peak.
I notice that the spectra look like those taken in RIKEN and not a single peak. In the 1GeV range I would interpret this as noise but since this |
Thu Apr 30 17:43:36 2015, Patrick Coleman-Smith, High Energy Spectra from LYCCA with pulser
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I have an eight FEE64 system now in place on the LYCCA chamber with a PB-5 pulser going into the adapter cards
test input. The test capacitor is 30pF.
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Thu Apr 30 20:21:20 2015, Patrick Coleman-Smith, High Energy Spectra from LYCCA with pulser
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> I have an eight FEE64 system now in place on the LYCCA chamber with a PB-5 pulser going into the adapter cards
> test input. The test capacitor is 30pF.
>
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Thu Apr 30 16:20:54 2015, JA, LHB, TD, AE, CG & VP, Friday 1 May 2015
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diode link threshold 0xca -> 0xb6
0x11 -> 0x2c
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Thu Apr 30 03:00:48 2015, TD, Degrader changes
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From 20.00 29.4.15
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Thu Apr 30 02:11:19 2015, TD, Example waveforms with heavy-ion beam 7x
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1 - nnaida1 DSSSD#3 p+n (pulser?)
2 - nnaida1 DSSSD#3 p+n heavy ion
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Thu Apr 30 01:06:44 2015, JA, LHB, TD, AE, CG & VP, Thursday 30 April 2015 16x
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Overnight
Degrader OUT
DAQ ran OK - data file R22
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Wed Apr 29 18:12:02 2015, AE, online analysis code 8x
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A first online analysis code is running now in Desktop 4 aidas1
The source code and executable are in
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Wed Apr 29 11:34:09 2015, Patrick Coleman-Smith, Fast Trigger timings against Pulser Input and LEC/MEC Fast Comparator threshold setting
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I have tried the latest version ( 26 ) of the FEE64 code and carried out some measurements of the Fast Trigger delay from the Pulser signal ( not the
Pulser Trigger out ) and observed the following.
The pulser gives a centroid of 28217 in the histogram. |
Wed Apr 29 11:00:29 2015, TD, Wednesday 29 April 2015 - R20 screenshots 10x
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1230: Attachments
19.00 Screenshots taken during R20 |
Wed Apr 29 10:01:27 2015, Patrick Coleman-Smith, Fast Trigger output fault in FEE64 FPGA logic
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The Fast Trigger output of the FEE64 is formed from the OR of the four OR16 signals ( one from each of the ASICs.
The logic levels of the OR16 signals are active low in the FPGA and so if the are OR'd together then the output is inactive if any one of the ASICs
is inactive. |
Wed Apr 29 01:03:41 2015, JA, LHB, TD, AE, CG & VP, Wednesday 29 April 2015 16x
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Overnight
Beam tuning, PID tests - beam stopped in scintilator detector + 1" thick Pb bricks
DAQ ran OK (not to disk)
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Tue Apr 28 11:22:25 2015, VP, RPI
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replace RPI with model B+. 4 USB ports + 4 port switch
The RPI system has been replaced by a model B+ which has 4 internal USB ports |
Tue Apr 28 06:25:13 2015, JA, LHB, TD, AE & CG, Tuesday 28th April progress 6x
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28/04/15
1420: Carried out ASIC optimisation tests to find best shaping time. Chose system wide shaping time of 0x6.
Waveforms of example FEEs/channels attachments 1-6. |
Tue Apr 28 05:59:48 2015, AE, "beta" trigger from MACB Trigger outputs 6x
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We've constructed a beta trigger with the signals from the p-side of the three DSSDs (OR of all fast
discriminator channels of each FEE).
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