ELOG - Tuesday 5 April

AIDA GELINA BRIKEN nToF CRIB ISOLDE CIRCE nTOFCapture DESPEC DTAS EDI_PSA 179Ta CARME StellarModelling DCF K40

DESPEC

Message ID: 410 Entry time: Tue Apr 5 08:52:16 2022

Author:	TD
Subject:	Tuesday 5 April

DSSSD bias OFF. DAQ STOPped

Attachment 1 FEE64 temps OK

Attachment 2 system wide checks OK *except* WR decoder (attachment 2) and FPGA ts errors no longer works

Attachment 6 System wide check - 'Synchronise ASIC clocks'

Attachment 5 System wide check - check ADC calibration - all 16x FEE64s fail

Attachment 4 System wide check - WR decoder status - aida09 WR status 0x10 clears

Repeat Synchronsie ASIC clocks

Attachment 3 System wide check - WR decoder status - aida05 WR status 0x10 clears

Attachment 1:

Screenshot_from_2022-04-05_09-52-42.png 167 kB Uploaded Tue Apr 5 09:53:50 2022 | Hide | Hide all

Attachment 2:

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Attachment 3:

Screenshot_from_2022-04-05_16-10-31.png 145 kB Uploaded Tue Apr 5 16:11:51 2022 | Hide | Hide all

Attachment 4:

Screenshot_from_2022-04-05_16-09-38.png 143 kB Uploaded Tue Apr 5 16:11:51 2022 | Hide | Hide all

Attachment 5:

Screenshot_from_2022-04-05_16-09-30.png 141 kB Uploaded Tue Apr 5 16:11:51 2022 | Hide | Hide all

Attachment 6:

Screenshot_from_2022-04-05_16-08-44.png 134 kB Uploaded Tue Apr 5 16:11:51 2022 | Hide | Hide all

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