 Thu Dec 19 14:07:38 2019, TD, Report - low - aida08 ADC spectrum size 32k cf. 64k channels expcted using layout 6x
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Note that aida08 spectrum 1.8.L size is (shown as) 32k channels cf. 64k channels expected using layout - attachment 1 - 5
Layout configuration - attachment 6
Why?
Current AIDA Options are shown below
[npg@aidas-gsi Options]$ pwd
/MIDAS/DB/EXPERIMENTS/AIDA/Options
[npg@aidas-gsi Options]$ csh
[npg@aidas-gsi Options]$ foreach f (`ls`)
foreach? echo $f
foreach? cat "$f"/CONTENTS
foreach? end
aida01
Index string Stat.offset&&Aida_Hist_W_Enable&&TS_SYNC_PHASE&&ExtClk&&Aida.shift&&MACB_TRIG_MODE&&Aida.offset&&RunNumber&&Aida_GroupBase&&Rate.channels&&Stat.channels&&Aida.Vchannels&&ASIC.settings&&Aida_Hist_D_Enable&&WAVE_DMA_HWM&&Stat.shift&&Aida.Wchannels&&Aida_Hist_V_Enable&&Include.Aida&&Aida.channels&&DataAcqPgm&&Aida_Hist_H_Enable&&DataFormat&&ASIC_DMA_HWM&&Aida_Hist_L_Enable
Stat.offset string 64
Aida_Hist_W_Enable string 1
MERGE.LinksInUse string 1%1%1%1%
Aida.shift string 0
TS_SYNC_PHASE string 0x0
ExtClk string 1
Aida.offset string 0
MACB_TRIG_MODE string 4
Stat.channels string 512
Rate.channels string 512
RunNumber string 12
Aida_GroupBase string 1
WAVE_DMA_HWM string 0x0007ffff
ASIC.settings string 2019Oct31-13.24.23
Aida.Vchannels string 256
Aida_Hist_D_Enable string 1
Aida.Wchannels string 1020
Stat.shift string 6
MERGE.LinksAvailable string 4
Include.Aida string 0
Aida_Hist_V_Enable string 0
Aida.channels string 65536
DataFormat string 0x0000
DataAcqPgm string AidaExecV9
Aida_Hist_H_Enable string 1
ASIC_DMA_HWM string 0x000fffff
Aida_Hist_L_Enable string 1
aida02
Index string Stat.offset&&Aida_Hist_W_Enable&&TS_SYNC_PHASE&&ExtClk&&Aida.shift&&MACB_TRIG_MODE&&Aida.offset&&RunNumber&&Aida_GroupBase&&Rate.channels&&Stat.channels&&Aida.Vchannels&&ASIC.settings&&Aida_Hist_D_Enable&&WAVE_DMA_HWM&&Stat.shift&&Aida.Wchannels&&Aida_Hist_V_Enable&&Include.Aida&&Aida.channels&&DataAcqPgm&&Aida_Hist_H_Enable&&DataFormat&&ASIC_DMA_HWM&&Aida_Hist_L_Enable
da_Hist_W_Enable&&TS_SYNC_PHASE&&ExtClk&&Aida.shift&&MACB_TRIG_MODE&&Aida.offset&&RunNumber&&Aida_GroupBase&&Rate.channels&&Stat.channels&&WAVE_DMA_HWM&&Aida_Hist_D_Enable&&ASIC.settings&&Aida.Vchannels&&Aida.Wchannels&&Stat.shift&&Aida.channels&&Include.Aida&&Aida_Hist_V_Enable&&DataFormat&&Aida_Hist_H_Enable&&DataAcqPgm&&ASIC_DMA_HWM&&Aida_Hist_L_Enable
Stat.offset string 64
Aida_Hist_W_Enable string 1
Aida.shift string 0
TS_SYNC_PHASE string 0x0
ExtClk string 1
Aida.offset string 0
MACB_TRIG_MODE string 4
Stat.channels string 512
RunNumber string 12
Rate.channels string 512
Aida_GroupBase string 1
Aida_Hist_D_Enable string 1
ASIC.settings string 2019Oct31-13.24.23
Aida.Vchannels string 256
WAVE_DMA_HWM string 0x0007ffff
Aida.Wchannels string 1020
Stat.shift string 6
Include.Aida string 0
Aida_Hist_V_Enable string 0
Aida.channels string 65536
DataFormat string 0x0000
DataAcqPgm string AidaExecV9
Aida_Hist_H_Enable string 1
ASIC_DMA_HWM string 0x000fffff
Aida_Hist_L_Enable string 1
aida03
Index string Stat.offset&&Aida_Hist_W_Enable&&TS_SYNC_PHASE&&ExtClk&&Aida.shift&&MACB_TRIG_MODE&&Aida.offset&&RunNumber&&Aida_GroupBase&&Rate.channels&&Stat.channels&&Aida.Vchannels&&ASIC.settings&&Aida_Hist_D_Enable&&WAVE_DMA_HWM&&Stat.shift&&Aida.Wchannels&&Aida_Hist_V_Enable&&Include.Aida&&Aida.channels&&DataAcqPgm&&Aida_Hist_H_Enable&&DataFormat&&ASIC_DMA_HWM&&Aida_Hist_L_Enable
Stat.offset string 64
Aida_Hist_W_Enable string 1
MERGE.LinksInUse string 1%1%1%1%
Aida.shift string 0
TS_SYNC_PHASE string 0x0
ExtClk string 1
Aida.offset string 0
MACB_TRIG_MODE string 4
Rate.channels string 512
Aida_GroupBase string 1
Stat.channels string 512
RunNumber string 12
Aida_Hist_D_Enable string 1
ASIC.settings string 2019Oct31-13.24.23
Aida.Vchannels string 256
WAVE_DMA_HWM string 0x0007ffff
Aida.Wchannels string 1020
Stat.shift string 6
MERGE.LinksAvailable string 4
Include.Aida string 0
Aida_Hist_V_Enable string 0
Aida.channels string 65536
DataFormat string 0x0000
DataAcqPgm string AidaExecV9
Aida_Hist_H_Enable string 1
ASIC_DMA_HWM string 0x000fffff
Aida_Hist_L_Enable string 1
aida04
Index string Stat.offset&&Aida_Hist_W_Enable&&TS_SYNC_PHASE&&ExtClk&&Aida.shift&&MACB_TRIG_MODE&&Aida.offset&&RunNumber&&Aida_GroupBase&&Rate.channels&&Stat.channels&&Aida.Vchannels&&ASIC.settings&&Aida_Hist_D_Enable&&WAVE_DMA_HWM&&Stat.shift&&Aida.Wchannels&&Aida_Hist_V_Enable&&Include.Aida&&Aida.channels&&DataAcqPgm&&Aida_Hist_H_Enable&&DataFormat&&ASIC_DMA_HWM&&Aida_Hist_L_Enable
Stat.offset string 64
Aida_Hist_W_Enable string 1
MERGE.LinksInUse string 1%1%1%1%
Aida.shift string 0
TS_SYNC_PHASE string 0x0
ExtClk string 1
Aida.offset string 0
MACB_TRIG_MODE string 4
Aida_GroupBase string 1
Rate.channels string 512
Stat.channels string 512
RunNumber string 12
WAVE_DMA_HWM string 0x0007ffff
Aida.Vchannels string 256
ASIC.settings string 2019Oct31-13.24.23
Aida_Hist_D_Enable string 1
Stat.shift string 6
Aida.Wchannels string 1020
MERGE.LinksAvailable string 4
Aida.channels string 65536
Aida_Hist_V_Enable string 0
Include.Aida string 0
Aida_Hist_H_Enable string 1
DataAcqPgm string AidaExecV9
DataFormat string 0x0000
ASIC_DMA_HWM string 0x000fffff
Aida_Hist_L_Enable string 1
aida05
Index string Stat.offset&&Aida_Hist_W_Enable&&TS_SYNC_PHASE&&ExtClk&&Aida.shift&&MACB_TRIG_MODE&&Aida.offset&&RunNumber&&Aida_GroupBase&&Rate.channels&&Stat.channels&&Aida.Vchannels&&ASIC.settings&&Aida_Hist_D_Enable&&WAVE_DMA_HWM&&Stat.shift&&Aida.Wchannels&&Aida_Hist_V_Enable&&Include.Aida&&Aida.channels&&DataAcqPgm&&Aida_Hist_H_Enable&&DataFormat&&ASIC_DMA_HWM&&Aida_Hist_L_Enable
Stat.offset string 64
Aida_Hist_W_Enable string 1
Aida.shift string 0
TS_SYNC_PHASE string 0x0
ExtClk string 1
Aida.offset string 0
MACB_TRIG_MODE string 4
RunNumber string 12
Rate.channels string 512
Aida_GroupBase string 1
Stat.channels string 512
WAVE_DMA_HWM string 0x0007ffff
Aida.Vchannels string 256
ASIC.settings string 2019Oct31-13.24.23
Aida_Hist_D_Enable string 1
Stat.shift string 6
Aida.Wchannels string 1020
Aida.channels string 65536
Aida_Hist_V_Enable string 0
Include.Aida string 0
Aida_Hist_H_Enable string 1
DataAcqPgm string AidaExecV9
DataFormat string 0x0000
ASIC_DMA_HWM string 0x000fffff
Aida_Hist_L_Enable string 1
aida06
Index string Stat.offset&&Aida_Hist_W_Enable&&TS_SYNC_PHASE&&ExtClk&&Aida.shift&&MACB_TRIG_MODE&&Aida.offset&&RunNumber&&Aida_GroupBase&&Rate.channels&&Stat.channels&&Aida.Vchannels&&ASIC.settings&&Aida_Hist_D_Enable&&WAVE_DMA_HWM&&Stat.shift&&Aida.Wchannels&&Aida_Hist_V_Enable&&Include.Aida&&Aida.channels&&DataAcqPgm&&Aida_Hist_H_Enable&&DataFormat&&ASIC_DMA_HWM&&Aida_Hist_L_Enable
Stat.offset string 64
Aida_Hist_W_Enable string 1
Aida.shift string 0
TS_SYNC_PHASE string 0x0
ExtClk string 1
Aida.offset string 0
MACB_TRIG_MODE string 4
RunNumber string 12
Rate.channels string 512
Aida_GroupBase string 1
Stat.channels string 512
Aida_Hist_D_Enable string 1
ASIC.settings string 2019Oct31-13.24.23
Aida.Vchannels string 256
WAVE_DMA_HWM string 0x0007ffff
Aida.Wchannels string 1020
Stat.shift string 6
Include.Aida string 0
Aida_Hist_V_Enable string 0
Aida.channels string 65536
DataFormat string 0x0000
DataAcqPgm string AidaExecV9
Aida_Hist_H_Enable string 1
ASIC_DMA_HWM string 0x000fffff
Aida_Hist_L_Enable string 1
aida07
Index string Stat.offset&&Aida_Hist_W_Enable&&TS_SYNC_PHASE&&ExtClk&&Aida.shift&&MACB_TRIG_MODE&&Aida.offset&&RunNumber&&Aida_GroupBase&&Rate.channels&&Stat.channels&&Aida.Vchannels&&ASIC.settings&&Aida_Hist_D_Enable&&WAVE_DMA_HWM&&Stat.shift&&Aida.Wchannels&&Aida_Hist_V_Enable&&Include.Aida&&Aida.channels&&DataAcqPgm&&Aida_Hist_H_Enable&&DataFormat&&ASIC_DMA_HWM&&Aida_Hist_L_Enable
Stat.offset string 64
Aida_Hist_W_Enable string 1
Aida.shift string 0
TS_SYNC_PHASE string 0x0
ExtClk string 1
Aida.offset string 0
MACB_TRIG_MODE string 4
RunNumber string 12
Rate.channels string 512
Aida_GroupBase string 1
Stat.channels string 512
Aida_Hist_D_Enable string 1
ASIC.settings string 2019Oct31-13.24.23
Aida.Vchannels string 256
WAVE_DMA_HWM string 0x0007ffff
Aida.Wchannels string 1020
Stat.shift string 6
Include.Aida string 0
Aida_Hist_V_Enable string 0
Aida.channels string 65536
DataFormat string 0x0000
DataAcqPgm string AidaExecV9
Aida_Hist_H_Enable string 1
ASIC_DMA_HWM string 0x000fffff
Aida_Hist_L_Enable string 1
aida08
Index string Stat.offset&&Aida_Hist_W_Enable&&TS_SYNC_PHASE&&ExtClk&&Aida.shift&&MACB_TRIG_MODE&&Aida.offset&&RunNumber&&Aida_GroupBase&&Rate.channels&&Stat.channels&&Aida.Vchannels&&ASIC.settings&&Aida_Hist_D_Enable&&WAVE_DMA_HWM&&Stat.shift&&Aida.Wchannels&&Aida_Hist_V_Enable&&Include.Aida&&Aida.channels&&DataAcqPgm&&Aida_Hist_H_Enable&&DataFormat&&ASIC_DMA_HWM&&Aida_Hist_L_Enable
Stat.offset string 64
Aida_Hist_W_Enable string 1
Aida.shift string 0
TS_SYNC_PHASE string 0x0
ExtClk string 1
Aida.offset string 0
MACB_TRIG_MODE string 4
RunNumber string 12
Rate.channels string 512
Aida_GroupBase string 1
Stat.channels string 512
WAVE_DMA_HWM string 0x0007ffff
Aida.Vchannels string 256
ASIC.settings string 2019Oct31-13.24.23
Aida_Hist_D_Enable string 1
Stat.shift string 6
Aida.Wchannels string 1020
Aida.channels string 65536
Aida_Hist_V_Enable string 0
Include.Aida string 0
Aida_Hist_H_Enable string 1
DataAcqPgm string AidaExecV9
DataFormat string 0x0000
ASIC_DMA_HWM string 0x000fffff
Aida_Hist_L_Enable string 1
aida09
Index string Stat.offset&&Aida_Hist_W_Enable&&TS_SYNC_PHASE&&ExtClk&&Aida.shift&&MACB_TRIG_MODE&&Aida.offset&&RunNumber&&Aida_GroupBase&&Rate.channels&&Stat.channels&&Aida.Vchannels&&ASIC.settings&&Aida_Hist_D_Enable&&WAVE_DMA_HWM&&Stat.shift&&Aida.Wchannels&&Aida_Hist_V_Enable&&Include.Aida&&Aida.channels&&DataAcqPgm&&Aida_Hist_H_Enable&&DataFormat&&ASIC_DMA_HWM&&Aida_Hist_L_Enable
Stat.offset string 64
Aida_Hist_W_Enable string 1
Aida.shift string 0
TS_SYNC_PHASE string 0x0
ExtClk string 1
0x0006dead string 0x0000
Aida.offset string 0
MACB_TRIG_MODE string 4
RunNumber string 12
Rate.channels string 512
Aida_GroupBase string 1
Stat.channels string 512
WAVE_DMA_HWM string 0x0007ffff
Aida.Vchannels string 256
ASIC.settings string 2019Oct31-13.24.23
Aida_Hist_D_Enable string 1
Stat.shift string 6
Aida.Wchannels string 1020
Aida.channels string 65536
Aida_Hist_V_Enable string 0
Include.Aida string 0
Aida_Hist_H_Enable string 1
DataAcqPgm string AidaExecV9
DataFormat string 0x0000
ASIC_DMA_HWM string 0x000fffff
Aida_Hist_L_Enable string 1
aida10
Index string Stat.offset&&Aida_Hist_W_Enable&&TS_SYNC_PHASE&&ExtClk&&Aida.shift&&MACB_TRIG_MODE&&Aida.offset&&RunNumber&&Aida_GroupBase&&Rate.channels&&Stat.channels&&Aida.Vchannels&&ASIC.settings&&Aida_Hist_D_Enable&&WAVE_DMA_HWM&&Stat.shift&&Aida.Wchannels&&Aida_Hist_V_Enable&&Include.Aida&&Aida.channels&&DataAcqPgm&&Aida_Hist_H_Enable&&DataFormat&&ASIC_DMA_HWM&&Aida_Hist_L_Enable
Stat.offset string 64
Aida_Hist_W_Enable string 1
Aida.shift string 0
TS_SYNC_PHASE string 0x0
ExtClk string 1
0x0006dead string 0x0000
Aida.offset string 0
MACB_TRIG_MODE string 4
Stat.channels string 512
RunNumber string 12
Rate.channels string 512
Aida_GroupBase string 1
Aida_Hist_D_Enable string 1
ASIC.settings string 2019Oct31-13.24.23
Aida.Vchannels string 256
WAVE_DMA_HWM string 0x0007ffff
Aida.Wchannels string 1020
Stat.shift string 6
Include.Aida string 0
Aida_Hist_V_Enable string 0
Aida.channels string 65536
DataFormat string 0x0000
DataAcqPgm string AidaExecV9
Aida_Hist_H_Enable string 1
ASIC_DMA_HWM string 0x000fffff
Aida_Hist_L_Enable string 1
aida11
Index string Stat.offset&&Aida_Hist_W_Enable&&TS_SYNC_PHASE&&ExtClk&&Aida.shift&&MACB_TRIG_MODE&&Aida.offset&&RunNumber&&Aida_GroupBase&&Rate.channels&&Stat.channels&&WAVE_DMA_HWM&&Aida_Hist_D_Enable&&ASIC.settings&&Aida.Vchannels&&Aida.Wchannels&&Stat.shift&&Aida.channels&&Include.Aida&&Aida_Hist_V_Enable&&DataFormat&&Aida_Hist_H_Enable&&DataAcqPgm&&ASIC_DMA_HWM&&Aida_Hist_L_Enable
Stat.offset string 64
Aida_Hist_W_Enable string 1
MERGE.LinksInUse string 1%1%1%1%
Aida.shift string 0
TS_SYNC_PHASE string 0x0
ExtClk string 1
Aida.offset string 0
MACB_TRIG_MODE string 4
Rate.channels string 512
Aida_GroupBase string 1
Stat.channels string 512
RunNumber string 12
Aida_Hist_D_Enable string 1
ASIC.settings string 2019Oct31-13.24.23
Aida.Vchannels string 256
WAVE_DMA_HWM string 0x0007ffff
Aida.Wchannels string 1020
Stat.shift string 6
MERGE.LinksAvailable string 4
Include.Aida string 0
Aida_Hist_V_Enable string 0
Aida.channels string 65536
DataFormat string 0x0000
DataAcqPgm string AidaExecV9
Aida_Hist_H_Enable string 1
ASIC_DMA_HWM string 0x000fffff
Aida_Hist_L_Enable string 1
aida12
Index string Stat.offset&&Aida_Hist_W_Enable&&TS_SYNC_PHASE&&ExtClk&&Aida.shift&&MACB_TRIG_MODE&&Aida.offset&&RunNumber&&Aida_GroupBase&&Rate.channels&&Stat.channels&&Aida.Vchannels&&ASIC.settings&&Aida_Hist_D_Enable&&WAVE_DMA_HWM&&Stat.shift&&Aida.Wchannels&&Aida_Hist_V_Enable&&Include.Aida&&Aida.channels&&DataAcqPgm&&Aida_Hist_H_Enable&&DataFormat&&ASIC_DMA_HWM&&Aida_Hist_L_Enable
Stat.offset string 64
Aida_Hist_W_Enable string 1
Aida.shift string 0
TS_SYNC_PHASE string 0x0
ExtClk string 1
Aida.offset string 0
MACB_TRIG_MODE string 4
RunNumber string 12
Rate.channels string 512
Aida_GroupBase string 1
Stat.channels string 512
WAVE_DMA_HWM string 0x0007ffff
Aida.Vchannels string 256
ASIC.settings string 2019Oct31-13.24.23
Aida_Hist_D_Enable string 1
Stat.shift string 6
Aida.Wchannels string 1020
Aida.channels string 65536
Aida_Hist_V_Enable string 0
Include.Aida string 0
Aida_Hist_H_Enable string 1
DataAcqPgm string AidaExecV9
DataFormat string 0x0000
ASIC_DMA_HWM string 0x000fffff
Aida_Hist_L_Enable string 1 |
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Fri Feb 21 12:16:06 2020, TD, NH, Report - high - unusual FEE64 crash during startup
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Wed Apr 3 12:09:47 2024, NH, Report - aida06 frequently fails to boot first time (PHY error)
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When booting up AIDA aida06 usually crashes the first time, it fails to get IP from DHCP
After 180 seconds it reboots and seems to connect fine
Log file attached, key part (to me) is this:
27:03:24/14:13:19|Sending DHCP requests .
27:03:24/14:13:21|eth0: XLlTemac: PHY Link carrier lost.
27:03:24/14:13:21|..... timed out!
27:03:24/14:14:33|IP-Config: Reopening network devices...
27:03:24/14:14:33|eth0: XLlTemac: Options: 0x3fa
27:03:24/14:14:34|eth0: XLlTemac: allocating interrupt 19 for dma mode tx.
27:03:24/14:14:34|eth0: XLlTemac: allocating interrupt 18 for dma mode rx.
27:03:24/14:14:34|eth0: XLlTemac: speed set to 1000Mb/s
27:03:24/14:14:36|eth0: XLlTemac: Send Threshold = 24, Receive Threshold = 4
27:03:24/14:14:36|eth0: XLlTemac: Send Wait bound = 254, Receive Wait bound = 254
27:03:24/14:14:36|Sending DHCP requests ......
27:03:24/14:26:16| |
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Wed Jan 8 10:46:50 2025, TD, Report - aida06 -boot fail due to network issue
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8:01:25/11:42:48|0x000000d00000-0x000000fe0000 : "user_kernel"
08:01:25/11:42:48|0x000000fe0000-0x000001000000 : "env_variables"
08:01:25/11:42:48|xilinx-xps-spi 81400400.hd-xps-spi: at 0x81400400 mapped to 0xD1028400, irq=20
08:01:25/11:42:48|SPI: XIlinx spi: bus number now 32766
08:01:25/11:42:48|xilinx-xps-spi 81400000.xps-spi: at 0x81400000 mapped to 0xD102C000, irq=21
08:01:25/11:42:48|SPI: XIlinx spi: bus number now 32765
08:01:25/11:42:48|mice: PS/2 mouse device common for all mice
08:01:25/11:42:48|Device Tree Probing 'i2c'
08:01:25/11:42:48| #0 at 0x81600000 mapped to 0xD1030000, irq=22
08:01:25/11:42:48|at24 0-0050: 1024 byte 24c08 EEPROM (writable)
08:01:25/11:42:48|TCP cubic registered
08:01:25/11:42:48|NET: Registered protocol family 17
08:01:25/11:42:48|RPC: Registered udp transport module.
08:01:25/11:42:49|RPC: Registered tcp transport module.
08:01:25/11:42:49|eth0: XLlTemac: Options: 0x3fa
08:01:25/11:42:49|eth0: XLlTemac: allocating interrupt 19 for dma mode tx.
08:01:25/11:42:49|eth0: XLlTemac: allocating interrupt 18 for dma mode rx.
08:01:25/11:42:49|eth0: XLlTemac: speed set to 1000Mb/s
08:01:25/11:42:51|eth0: XLlTemac: Send Threshold = 24, Receive Threshold = 4
08:01:25/11:42:51|eth0: XLlTemac: Send Wait bound = 254, Receive Wait bound = 254
08:01:25/11:42:51|Sending DHCP requests .
08:01:25/11:42:53|eth0: XLlTemac: PHY Link carrier lost.
08:01:25/11:42:53|..... timed out!
08:01:25/11:44:15|IP-Config: Reopening network devices...
08:01:25/11:44:15|eth0: XLlTemac: Options: 0x3fa
08:01:25/11:44:16|eth0: XLlTemac: allocating interrupt 19 for dma mode tx.
08:01:25/11:44:16|eth0: XLlTemac: allocating interrupt 18 for dma mode rx.
08:01:25/11:44:16|eth0: XLlTemac: speed set to 1000Mb/s
08:01:25/11:44:18|eth0: XLlTemac: Send Threshold = 24, Receive Threshold = 4
08:01:25/11:44:18|eth0: XLlTemac: Send Wait bound = 254, Receive Wait bound = 254
08:01:25/11:44:18|Sending DHCP requests ...... timed out!
08:01:25/11:45:35|IP-Config: Auto-configuration of network failed.
08:01:25/11:45:35|Root-NFS: No NFS server available, giving up.
08:01:25/11:45:35|VFS: Unable to mount root fs via NFS, trying floppy.
08:01:25/11:45:35|VFS: Cannot open root device "nfs" or unknown-block(2,0)
08:01:25/11:45:35|Please append a correct "root=" boot option; here are the available partitions:
08:01:25/11:45:35|Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(2,0)
08:01:25/11:45:35|Call Trace:
08:01:25/11:45:35|[c6827ed0] [c0005de8] show_stack+0x44/0x16c (unreliable)
08:01:25/11:45:35|[c6827f10] [c00345bc] panic+0x94/0x168
08:01:25/11:45:35|[c6827f60] [c0341d34] mount_block_root+0x12c/0x244
08:01:25/11:45:36|[c6827fb0] [c03420d8] prepare_namespace+0x17c/0x208
08:01:25/11:45:36|[c6827fd0] [c0341220] kernel_init+0x104/0x130
08:01:25/11:45:36|[c6827ff0] [c000e140] kernel_thread+0x4c/0x68
08:01:25/11:45:36|Rebooting in 180 seconds.. |
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Wed Apr 10 14:53:50 2019, NH, Report - FEE stops sending data 6x
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it seems a FEE somtimes enters a confusing state and stops sending data
the current merger requires all FEEs to be active and so this stops the entire system from proceeding.
On MIDAS the page reports the module is "undefined"
On the TTY console (PUTTY) it returns: do_GetState returned z=0 and 8
Resetting the DAQ in question via MIDAS works (Putty logs of the stages shown) and then the merger resumes without trouble. |
 Fri Apr 12 15:15:33 2019, NH, Report - FEE Kernel Panics (Update on 48)
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Update on issue #48 - the "confusing state" is that the FEE has restarted and hence is undefined again.
An attached TTY log from the pi shows that the module is kernel panicking.
I have seen a couple of FEEs panic with the same error now.
(NB. The Day/time of the logs is wrong as the pi does not have the correct time - pis dont have a RTC or Internet access so the time isn't corrected)
Temperature of the modules is fine.
Aida is currently powered off (and I am away from GSI)
| Quote: |
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it seems a FEE somtimes enters a confusing state and stops sending data
the current merger requires all FEEs to be active and so this stops the entire system from proceeding.
On MIDAS the page reports the module is "undefined"
On the TTY console (PUTTY) it returns: do_GetState returned z=0 and 8
Resetting the DAQ in question via MIDAS works (Putty logs of the stages shown) and then the merger resumes without trouble.
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Fri Nov 1 14:17:15 2019, Nic, Patrick, Reply: WR Timestamps
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> > All 12 FEEs have valid WR Timestamps
> > Had to powercycle aida09 once as before raw readout was displaying upper 12 bits of WR timestamp as 0. Unsure of other method.
> >
> > HDMI cables in aida09 checked and good.
>
> The problem would be the cable , one end or the other.
> I think ( if I recall ) a setup would restart the WR decoder.
>
> I notice you have set the WR info word rate to be quite high , 6123/sec typ, is this intentional ?
Cable will be replaced once a spare is available.
Setup did not restart the WR decoder when this problem occurred beforehand - Reset/Setup tried.
WR rate was chosen by Vic I believe, I am unsure of reasoning myself. |
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Thu Nov 7 10:22:26 2019, Nic, Patrick, Reply: WR Timestamps
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> > > All 12 FEEs have valid WR Timestamps
> > > Had to powercycle aida09 once as before raw readout was displaying upper 12 bits of WR timestamp as 0. Unsure of other method.
> > >
> > > HDMI cables in aida09 checked and good.
> >
> > The problem would be the cable , one end or the other.
> > I think ( if I recall ) a setup would restart the WR decoder.
> >
> > I notice you have set the WR info word rate to be quite high , 6123/sec typ, is this intentional ?
>
> Cable will be replaced once a spare is available.
>
> Setup did not restart the WR decoder when this problem occurred beforehand - Reset/Setup tried.
>
> WR rate was chosen by Vic I believe, I am unsure of reasoning myself.
An update/clarification:
Although the upper bits are zero I believe actually it is a total failure to synchronise to WR:
aida09
WR Time Item 0x80500000 0x0fbd8000; Time (48:63)=0x0; Time (28:47)=0x249; Time (0:27)=0x0fbd8000
WR Time Item 0x80400249 0x0fbd8000; Time (28:47)=0x249; Time (0:27)=0x0fbd8000
WR Time Item 0x80500000 0x0fbdc000; Time (48:63)=0x0; Time (28:47)=0x249; Time (0:27)=0x0fbdc000
WR Time Item 0x80400249 0x0fbdc000; Time (28:47)=0x249; Time (0:27)=0x0fbdc000
WR Time Item 0x80500000 0x0fbe0000; Time (48:63)=0x0; Time (28:47)=0x249; Time (0:27)=0x0fbe0000
WR Time Item 0x80400249 0x0fbe0000; Time (28:47)=0x249; Time (0:27)=0x0fbe0000
aida10
WR Time Item 0x8050022e 0x0bde8000; Time (48:63)=0x22e; Time (28:47)=0xe29d5; Time (0:27)=0x0bde8000
WR Time Item 0x804e29d5 0x0bde8000; Time (28:47)=0xe29d5; Time (0:27)=0x0bde8000
WR Time Item 0x8050022e 0x0bdec000; Time (48:63)=0x22e; Time (28:47)=0xe29d5; Time (0:27)=0x0bdec000
WR Time Item 0x804e29d5 0x0bdec000; Time (28:47)=0xe29d5; Time (0:27)=0x0bdec000
WR Time Item 0x8050022e 0x0bdf0000; Time (48:63)=0x22e; Time (28:47)=0xe29d5; Time (0:27)=0x0bdf0000
WR Time Item 0x804e29d5 0x0bdf0000; Time (28:47)=0xe29d5; Time (0:27)=0x0bdf0000 |
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Wed Aug 14 12:40:11 2024, JB, Repaired DSSSD delivery 14.09.2024 11x
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Three BB18-1000 triples AIDAs collected on 14.09.2024
Find attached visual of the wafer and bond wire + factory bias tests accompanying the DSSSDs. elog:669/1 elog:669/2 elog:669/3
Visual inspection carried out showed that bond wires have been fixed + fingerprint on one DSSSD removed and wires repaired. elog:669/4 elog:669/5 elog:669/6 elog:669/7 elog:669/8 elog:669/9 elog:669/10 elog:669/11
DSSSD 1 (defect bias issue 80V): 3208-10 / 3208-18 / 3208-20
DSSSD 2 (3208-6 dysfunctional): 3208-6 / 3208-9 / 3208-16
DSSSD 3 (defect fingerprint): 3131-5 / 3131-10 / 3131-12
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Mon Mar 16 01:07:29 2020, TA, AM, ES, Regular entry 13x
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02:14 all system wide checks okay
FEE temperatures okay
leakage currents okay and recorded to spreadsheet
good event stats okay
merger running at 3M items/sec
tape service running at 26MB/sec
All attached to this entry with screenshots to 1-7
04:05 all system wide checks okay
FEE temperatures okay
leakage currents okay and recorded to spreadsheet
good event stats okay
merger running at 3M items/sec
tape service running at 26MB/sec
All attached tp this entry with screenshots 7-14 |
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Mon Mar 16 05:08:12 2020, TA, AM, ES, Regular entry 6x
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02:14 all system wide checks okay
FEE temperatures okay
leakage currents okay and recorded to spreadsheet
good event stats okay
merger running at around 3M items/sec
tape service running at 26MB/sec
All attached to this entry with screenshots to 1-7 |
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Thu May 12 21:43:49 2022, BA, MA, Rates
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Statistic check (screenshot attached).
Temperatures OK (screenshot attached).
Bias and leakage currents OK (same screenshot as temps).
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Sat Dec 8 15:22:52 2018, TD, Raspberry Pi startup
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nnrpi1 - FEE64 system consoles
nnrpi2 - USB-controlled ac mains relay, CAEN N1419ET
username: pi
password: *******
To startup TclHttpd server for web access via port 8015 execute
/MIDAS/TclHttpd/Linux-arm/TclHttpd-server
Update - 9 March 2020 command line should be
/MIDAS/TclHttpd/linux-arm/TclHttpd-server |
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Fri Jan 25 12:26:17 2019, NH, Raspberry Pi Startup & Information
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Two raspberry pis:
nnrpi1 - FEE64 system consoles
nnrpi2 - AC Mains Relay & CAEN HV
Startup:
1. Plug in micro-USB on pis
2. Connect via ssh: ssh pi@nnrpi1 or ssh pi@nnrpi2
3. Start MIDAS:
cd /MIDAS/TclHttpd/Linux-arm
./TclHttpd-server
4. Connect from aida-gsi web browser
http://nnrpi2:8015 - For AC Relay Control
http://nnrpi1:8015 - For Pi Monitoring (Get list of USB terminals, Connect)
-> Parse USB log for details to check if all FEEs have finished booting completely or not
5. For CAEN HV connect via ssh/X (ssh -X pi@nnrpi2) and run
putty &
Opens putty window to connect to the CAEN HV module (Serial /dev/ttyACM0) |
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Thu Oct 31 09:36:37 2019, TD, RIKEN LayOut directory
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Fri Nov 7 12:30:30 2025, JB, GB, MP, Pulser walkthrough for source tests.
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13:30 We are going to do the pulser walkthrough for the the source tests.
We are wrapping the snout in some copper first to further establish a better connection with the ground.
2025Nov07-13.55.01 is a setting with 100 keV threshold across all FEEs.
We got the DAQ running, TEMPS ok and biased OK. We execute the pulser walkthrough as follow:
10x attenuation - 10V -> 1V in steps of 1 V
/lustre/despec/aida_sourcetest_2025/raw/
pulser_wt_10V - 10V
pulser_wt_9V - 9V
pulser_wt_8V - 8V
pulser_wt_7V - 7V
pulser wt_6V - 6V
pulser_wt_5V - 5V
pulser_wt_4V - 4V
pulser_wt_3V - 3V
pulser_wt_2V - 2V
pulser_wt_1V - 1V
Data taking stopped and we turn off the system to a safe state.
Initial analysis of the raw ADC spectra can be seen in attachment 4 & 5. |
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Thu Apr 4 14:07:45 2019, NH, Pulser Configuration
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Pulser settings during April run:
Rate 2Hz
Delay 250 NS
Amplitude 1 V
Fall 1 ms
Polarity Pos
Pulse Top Tail
Attenuation 1X
PB5 Pulse On
Clamp Off
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Mon Oct 18 13:01:04 2021, OH, Proxy config
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Proxy for firefox and anydesk |
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Thu Sep 8 12:37:18 2022, NH, Proxy Port Changed
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The proxy in Firefox, Yum and AnyDesk has been changed as the old wasn't working
proxy.gsi.de port 3128 is now in use |
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Wed Apr 28 17:39:35 2021, TD, Preparations for setup of aida13-aida16
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Updated /etc/dhcpd.conf
cd /etc
cp dhcpd.conf dhcpd.conf.BAK-280421
Add MAC addresses https://elog.ph.ed.ac.uk/DESPEC/285
aida13 xilinx_lltemac 81c00000.ethernet: MAC address is now d8:80:39:42: d:15
aida14 xilinx_lltemac 81c00000.ethernet: MAC address is now d8:80:39:42: d: b
aida15 xilinx_lltemac 81c00000.ethernet: MAC address is now d8:80:39:41:ee:10
aida16 xilinx_lltemac 81c00000.ethernet: MAC address is now d8:80:39:41:f6:ed
New version of dhcpd.conf (and backup) - attachments 1 & 2
Cannot find dhcpd (and therefore re-read config and restart) in System - Administration -> Services
- has the dhcpd service been re-named or amalgamated with another service?
Updated /MIDAS/config/TclHttpd/aidas-gsi@8015/startup.tcl
New version of startup.tcl (and backup) - attachments 3 & 4
Created rfs filesytems for aida13-aida24
[root@aidas-gsi]# cd /home/Embedded/XilinxLinux/ppc_4xx/rfs
[root@aidas-gsi rfs]# cd aida01
[root@aidas-gsi rfs]# tar cvf ../rfs.tar .
Create directories aida13-aida24, uid=10101, gid=npg, mode 777
[root@aidas-gsi rfs]# cd aida13; tar xvf ../rfs.tar .
:
:
etc
[root@aidas-gsi rfs]# ls -l
total 1491880
drwxrwxrwx. 19 10101 npg 4096 Apr 28 16:32 aida01
drwxrwxrwx. 19 10101 npg 4096 Apr 28 16:32 aida02
drwxrwxrwx. 19 10101 npg 4096 Apr 28 16:32 aida03
drwxrwxrwx. 19 10101 npg 4096 Apr 24 03:51 aida04
drwxrwxrwx. 19 10101 npg 4096 Apr 24 03:51 aida05
drwxrwxrwx. 19 10101 npg 4096 Apr 28 16:32 aida06
drwxrwxrwx. 19 10101 npg 4096 Apr 28 16:32 aida07
drwxrwxrwx. 19 10101 npg 4096 Apr 28 16:32 aida08
drwxrwxrwx. 19 10101 npg 4096 Apr 28 16:35 aida09
drwxrwxrwx. 19 10101 npg 4096 Apr 28 16:32 aida10
drwxrwxrwx. 19 10101 npg 4096 Apr 28 16:34 aida11
drwxrwxrwx. 19 10101 npg 4096 Apr 28 16:32 aida12
drwxrwxrwx. 19 10101 npg 4096 Apr 28 16:32 aida13
drwxrwxrwx. 19 10101 npg 4096 Apr 28 16:32 aida14
drwxrwxrwx. 19 10101 npg 4096 Apr 28 16:32 aida15
drwxrwxrwx. 19 10101 npg 4096 Apr 28 16:32 aida16
drwxrwxrwx. 19 10101 npg 4096 Apr 28 16:32 aida17
drwxrwxrwx. 19 10101 npg 4096 Apr 28 16:32 aida18
drwxrwxrwx. 19 10101 npg 4096 Apr 28 16:32 aida19
drwxrwxrwx. 19 10101 npg 4096 Apr 28 16:32 aida20
drwxrwxrwx. 19 10101 npg 4096 Apr 28 16:32 aida21
drwxrwxrwx. 19 10101 npg 4096 Apr 28 16:32 aida22
drwxrwxrwx. 19 10101 npg 4096 Apr 28 16:32 aida23
drwxrwxrwx. 19 10101 npg 4096 Apr 28 16:32 aida24
-rw-r--r--. 1 root root 1527582720 Apr 28 18:26 rfs.tar
Once dhcpd has been restarted it should be possible to power cycle all FEE64s, start system
and update firmware of newly installed FEE64s. |