| ID |
Date |
Author |
Subject |
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42
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Tue Apr 2 09:42:20 2019 |
NH | MBS Server setup |
MBS is currently configured and accepting data:
x86l-94 : AIDA Foreign data receiver
x86l-4 : DESPEC Time sorter
The time sorter is complaining about AIDA time warps (around 1 Hz) it is assumed this is related to other merger / timestamping issues being worked on by Vic |
|
40
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Mon Apr 1 10:20:20 2019 |
CA, NH, TD | MBS Relay startup |
To start the MBS Data Relay, click on the top rightmost of the MIDAS icons (MBS relay, Data Relay => MBS) in
Desktop 3. (attachment 1)
This will bring up the Data Relay MBS terminal.
Ensure the path defined in the datarelaymbs is set to the correct directory (shown in attachment 2) |
| Attachment 1: mbsrealaypic.png
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| Attachment 2: mbscommand.png
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22
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Thu Jan 24 17:16:32 2019 |
CA, TD, NH, VP | MACB time switch settings |
AIDA@DESPEC MACB time switch settings before and after WR are as follows.
Attachment 1 - MACB 1-4 from left to right
MACB number: 1 2 3 4
100MHZ clock setting (before WR): 0 2 2 2
White Rabbit setting (after WR): 3 3 3 3 |
| Attachment 1: 50668223_286084358731841_9104059387265155072_n.jpg
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| Attachment 2: despecmacb.pdf
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517
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Wed Jan 18 13:40:33 2023 |
PJCS TD | MACB settings with either Emulator or VITAR |
When using the VETAR connected to the HDMI port of the root MACB the settings for all the MACB in the system 0x3.
This setting takes the Clock and Data line from the input HDMI and outputs it via teh HDMI output ports.
When using the Emulator connected via the SMA connectors on the back of the root MACB then the setting for the root MACB should be 0xD and all others should be 0x3.
Attached is the .jed file for programming the MACB and the .vhd source file to help with understanding of the settings. |
| Attachment 1: macb_apr20.jed
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| Attachment 2: macb_apr20.vhd
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:03:27 03/16/2011
-- Design Name:
-- Module Name: macb_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
-- NOTE all in/out notations are relative to this unit
entity macb_apr20 is
Port (
port1_sp : inout STD_LOGIC_VECTOR (3 downto 0);
port2_sp : inout STD_LOGIC_VECTOR (3 downto 0);
port3_sp : inout STD_LOGIC_VECTOR (3 downto 0);
port4_sp : inout STD_LOGIC_VECTOR (3 downto 0);
layer_sp : inout STD_LOGIC_VECTOR (3 downto 0);
layer_trigger : out std_logic ;
sync_return : in STD_LOGIC_VECTOR (3 downto 1);
selector : in STD_LOGIC_VECTOR (3 downto 0);
sync_select : out STD_LOGIC_vector(1 downto 0 );
clock200_select : out STD_LOGIC_vector( 1 downto 0 ) ;
butis_divide_reset : out std_logic ;
butis_divide_s : out std_logic_vector( 2 downto 0 ) ;
clock_5 : in std_logic ;
sync_5 : in std_logic ;
trigger : in std_logic_vector( 3 downto 0 ) ;
MBS_in : in STD_LOGIC_VECTOR (3 downto 0);
MBS_out : out STD_LOGIC_VECTOR (3 downto 0));
end macb_apr20;
architecture Behavioral of macb_apr20 is
signal port1_spi : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port1_spo : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port1_t : STD_LOGIC_VECTOR (3 downto 0) := ( others => '1' );
signal port2_spi : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port2_spo : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port2_t : STD_LOGIC_VECTOR (3 downto 0) := ( others => '1' );
signal port3_spi : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port3_spo : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port3_t : STD_LOGIC_VECTOR (3 downto 0) := ( others => '1' );
signal port4_spi : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port4_spo : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port4_t : STD_LOGIC_VECTOR (3 downto 0) := ( others => '1' );
signal layer_spi : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal layer_spo : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal layer_t : STD_LOGIC_VECTOR (3 downto 0) := ( others => '1' );
signal seli : integer range 0 to 15 := 0 ;
-- well really
signal MBS_in_n : std_logic_vector( 3 downto 0 ) := "0000" ;
begin
MBS_in_n <= ( not MBS_in);
seli <= conv_integer(not selector) ;
-- MBS signal allocations to sp lines and HDMI pin. This maps to NIM connections
-- 0 : MBS_clock10 SP0 13
-- 1 : MBS_reset SP1 14
-- 2 : MBS_reset_rq SP2 15
-- 3 : MBS_Trigger SP3 16
layer_trigger <= trigger(0) or trigger(1) or trigger(2) or trigger(3) ;
-- divider controls set for pass-through
butis_divide_reset <= '1' ; -- for now don't reset ;
process ( seli , MBS_in_n, port1_spi, port2_spi, port3_spi, port4_spi, layer_spi, sync_return ,sync_5 )
-- note : & => concatenate
begin
case seli is
when 0 => --- Master/ Root / MBS / Internal clock
port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= ( others => '0' ) ;
layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
sync_select <= "00" ; -- select sync from port 1
clock200_select <= "00" ; -- select internal 200 MHz oscillator
MBS_out <= MBS_in_n(3) & MBS_in_n(2) & port1_spi(1) & port1_spi(0) ;
butis_divide_s <= "000" ; -- s2 is 0 for pass,
when 1 => --- Master/ Root / MBS / BuTiS clock and SYNC
port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= ( others => '0' ) ;
layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
sync_select <= "01" ; -- select sync from external using SMA input
clock200_select <= "01" ; -- select external 200 MHz oscillator using SMA input
MBS_out <= MBS_in_n(3) & MBS_in_n(2) & port1_spi(1) & port1_spi(0) ;
butis_divide_s <= "000" ; -- s2 is 0 for pass,
when 2 => --- Master/ Branch / MBS / Next layer clock next layer SYNC
port1_spo <= layer_spi(3) & layer_spi(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= layer_spi(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= layer_spi(3) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= layer_spi(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= '0' & '0' & port1_spi(1) & port1_spi(0) ; -- drive the clock and reset down a layer
layer_t <= "1100" ; -- just drive the bottom two bits to the "next" port
sync_select <= "10" ; -- select sync from next_layer
clock200_select <= "10" ; -- select clock from next layer
MBS_out <= layer_spi(3) & layer_spi(2) & port1_spi(1) & port1_spi(0) ;
butis_divide_s <= "000" ; -- s2 is 0 for pass,
when 3 => --- Slave / Branch / MBS / Next layer clock and sync
port1_spo <= layer_spi(3) & '0' & layer_spi(1) & layer_spi(0);
port1_t <= "0100" ; -- drive clock, reset, trigger only
port2_spo <= layer_spi(3) & '0' & layer_spi(1) & layer_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= layer_spi(3) & '0' & layer_spi(1) & layer_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= layer_spi(3) & '0' & layer_spi(1) & layer_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= '0' & '0' & '0' & '0' ; -- drive nothing
layer_t <= "1111" ; -- just drive nothing down
sync_select <= "10" ; -- select sync from next layer
clock200_select <= "10" ; -- select clock from next layer
MBS_out <= layer_spi ; -- map all the signals for monitoring ?
butis_divide_s <= "000" ; -- s2 is 0 for pass,
when 4 => --- Master/ Root / MBS / BuTiS clock / Internal SYNC / External timestamp reset
port1_spo <= MBS_in_n(3) & '0' & MBS_in_n(1) & '0' ;
port1_t <= "0100" ; -- drive clock, reset, trigger only
port2_spo <= MBS_in_n(3) & '0' & MBS_in_n(1) & '0' ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & MBS_in_n(1) & '0' ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & MBS_in_n(1) & '0' ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= ( others => '0' ) ;
layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
sync_select <= "00" ; -- select sync from port 1
clock200_select <= "01" ; -- select external 50 MHz oscillator using SMA input
MBS_out <= MBS_in_n(3) & MBS_in_n(2) & MBS_in_n(1) & sync_5 ;
butis_divide_s <= "000" ; -- s2 is 0 for pass,
when 5 => --- Master/ Root / MBS / External 50Mhz clock / Internal Sync
port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= ( others => '0' ) ;
layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
sync_select <= "00" ; -- select sync from port 1
clock200_select <= "01" ; -- select external SMA input
MBS_out <= MBS_in_n(3) & MBS_in_n(2) & port1_spi(1) & port1_spi(0) ;
butis_divide_s <= "000" ; -- s2 is 0 for pass through.
when 6 => --- Master/ Root / MBS / External 100Mhz clock / Internal Sync
port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= ( others => '0' ) ;
layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
sync_select <= "00" ; -- select sync from port 1
clock200_select <= "01" ; -- select external SMA input
MBS_out <= MBS_in_n(3) & MBS_in_n(2) & port1_spi(1) & port1_spi(0) ;
butis_divide_s <= "100" ; -- s2 is 1 for external, 00 for /2.
when 7 => --- Fast NIM input for each FEE / Next layer clock next layer SYNC
port1_spo <= MBS_in_n(0) & layer_spi(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(1) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(2) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= '0' & '0' & port1_spi(1) & port1_spi(0) ; -- drive the clock and reset down a layer
layer_t <= "1100" ; -- just drive the bottom two bits to the "next" port
sync_select <= "10" ; -- select sync from next_layer
clock200_select <= "10" ; -- select clock from next layer
MBS_out <= layer_spi(3) & layer_spi(2) & port1_spi(1) & port1_spi(0) ;
butis_divide_s <= "000" ; -- s2 is 0 for pass,
when 8 => --- Fast NIM input from Input 3 for each FEE / Next layer clock next layer SYNC
port1_spo <= MBS_in_n(3) & layer_spi(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= '0' & '0' & port1_spi(1) & port1_spi(0) ; -- drive the clock and reset down a layer
layer_t <= "1100" ; -- just drive the bottom two bits to the "next" port
sync_select <= "10" ; -- select sync from next_layer
clock200_select <= "10" ; -- select clock from next layer
MBS_out <= layer_spi(3) & layer_spi(2) & port1_spi(1) & port1_spi(0) ;
butis_divide_s <= "000" ; -- s2 is 0 for pass,
when 9 => --- Master/ Root / Internal clock / sync_returns to NIM
port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= ( others => '0' ) ;
layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
sync_select <= "00" ; -- select sync from port 1
clock200_select <= "00" ; -- select internal 200 MHz oscillator
MBS_out <= sync_return(3) & sync_return(2) & sync_return(1) & '0' ;
butis_divide_s <= "000" ; -- s2 is 0 for pass,
when 10 => --- Master/ Root / MBS / BuTiS clock /2 and SYNC
port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= "0000" ;
layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
sync_select <= "01" ; -- select sync from external using SMA input
clock200_select <= "01" ; -- select external 200 MHz oscillator using SMA input
MBS_out <= MBS_in_n ; -- for testing NIM I/O
butis_divide_s <= "100" ; -- s2 = 1 and s1,s0 decode to 00=>/2 , 01=>/4, /8 , /16
when 12 => --- Master/ Root / MBS / BuTiS clock /2 and SYNC
port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= ( others => '0' ) ;
layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
sync_select <= "01" ; -- select sync from external using SMA input
clock200_select <= "01" ; -- select external 200 MHz oscillator using SMA input
MBS_out <= MBS_in_n(3) & MBS_in_n(2) & port1_spi(1) & port1_spi(0) ;
butis_divide_s <= "100" ; -- s2 = 1 and s1,s0 decode to 00=>/2 , 01=>/4, /8 , /16
when 13 => --- Master/ Root / MBS / BuTiS clock /4 and SYNC
port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= ( others => '0' ) ;
layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
sync_select <= "01" ; -- select sync from external using SMA input
clock200_select <= "01" ; -- select external 200 MHz oscillator using SMA input
MBS_out <= MBS_in_n(3) & MBS_in_n(2) & port1_spi(1) & port1_spi(0) ;
butis_divide_s <= "101" ; -- s2 = 1 and s1,s0 decode to 01=>/4
when 14 => --- Master/ Root / MBS / BuTiS clock /8 and SYNC
port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
... 161 more lines ...
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| Attachment 3: zybo.jpg
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| Attachment 4: MACB.jpg
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Wed Jan 23 09:25:55 2019 |
CA, TD, NH, VP | MACB and setup pics 23.01.19 |
Pictures of leaking cooling pipe
MACB switch settings
AIDA mount - needs rotated
Attachment 11 - AIDA@DESPEC MACB settings - 100MHz and WR |
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| Attachment 11: despecmacb.pdf
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292
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Tue May 4 14:05:48 2021 |
NH | MACB Cables |
During the installation of the 4 new HDMI cables for aidas13-16 the HDMI cables between the MACB Root and the MACB leaves were looped through the cable guide at the top to support them more
This may improve their connection and reduce the chance of WR errors seen in S460/S452
The connectors were all reseated a few times to clean the contacts too |
| Attachment 1: macb_front.jpg
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| Attachment 2: macb_side.jpg
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435
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Thu May 12 22:49:39 2022 |
BA, MA | Low Rates |
The rate is very low in all aida, not sure . |
| Attachment 1: RatesLow2022-05-12_23-48-01.png
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441
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Fri May 13 06:56:14 2022 |
OH, BA, MA | Low Rates |
| Quote: |
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The rate is very low in all aida, not sure .
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This was because the statistics page had been changed to transfer buffers. The rates were ok |
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460
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Mon May 16 14:07:06 2022 |
TD | Lost activity monitor |
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| Attachment 1: Screenshot_from_2022-05-16_15-04-56.png
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539
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Fri Mar 15 16:29:57 2024 |
NH | Leakage currents |
The behaviour of the DSSSD leakage current at low voltages and during biases is unusual and varies depending on how the adapter boards are connected
To summarise the behaviour I have observed
Minimum bias configuration:
4 adapter boards, one n+n (LK1), three p+n (-ve bias), ground from n+n to one p+n
Voltage (and leakage current) unstable at low voltages, seems to settle at around -60 V
Drops can include 0 leakage current
Full adapter configuration:
8 adapter boards, ground ring complete
Same as minimum, but the drops seem to be much smaller (and not to 0 leakage current)
-60V again seems to be the turnover to a stable leakage current
In both cases the leakage current during ramping appears basically the same as when settled
Full into FEEs
8 adapter boards, fully connected to 8 FEEs
The leakage current is *much* higher during ramp,up to 17 uA near the end. No fluctuations
Once ramping has finished the current quickly drops back down and settles at the nominal leakage current
This has been observed in October/December too, it is not new (https://elog.ph.ed.ac.uk/AIDA/910)
During power up of the FEEs the current sometimes drops briefly (when the ASICs get programmed, I believe)
I think it is related to the ground (more or less current flowing through the HV supply instead of alternate paths?)
It should be kept in mind when testing new detectors to not worry about the detector at low voltages |
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686
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Thu Jan 9 16:25:51 2025 |
TD | LEC fast comparator threshold too low |
LEC fast comparator has been set to 0x2 (200keV) which is *very* low and means the fast comparator will be triggering on noise.
The *minimum* LEC fast comparator setting should be in the range 0x5 - 0xa (500-1000keV).
I have set the TapeServer to 'no storage' mode to avoid filling the aida-gsi disk with rubbish. |
| Attachment 1: Screenshot_from_2025-01-09_17-28-45.png
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687
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Thu Jan 9 17:36:50 2025 |
TD | LEC fast comparator threshold too low |
>
> LEC fast comparator has been set to 0x2 (200keV) which is *very* low and means the fast comparator will be triggering on noise.
>
> The *minimum* LEC fast comparator setting should be in the range 0x5 - 0xa (500-1000keV).
>
> I have set the TapeServer to 'no storage' mode to avoid filling the aida-gsi disk with rubbish.
Thanks. From the DESPEC elog.gsi.de/despec/Implantation+Stack/18
"We have made a trigger from the BGO logic and OR64 of the fast discriminator from AIDA. This was sent as a trigger to the bPlast Exploder.
This did not work as the FEE64s of AIDA are running into high dead-time and a result are dropping data. This is a problem for the ucesb unpacker as it will quite working if one of the subsystem stops sending data. (@Nic is this correct?)
This is indeed what I see as whenever we try to run FAIRROOT the tree builder exits immediately." |
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688
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Thu Jan 9 17:56:14 2025 |
TD | LEC fast comparator threshold too low |
> >
> > LEC fast comparator has been set to 0x2 (200keV) which is *very* low and means the fast comparator will be triggering on noise.
> >
> > The *minimum* LEC fast comparator setting should be in the range 0x5 - 0xa (500-1000keV).
> >
> > I have set the TapeServer to 'no storage' mode to avoid filling the aida-gsi disk with rubbish.
>
> Thanks. From the DESPEC elog.gsi.de/despec/Implantation+Stack/18
>
> "We have made a trigger from the BGO logic and OR64 of the fast discriminator from AIDA. This was sent as a trigger to the bPlast Exploder.
>
> This did not work as the FEE64s of AIDA are running into high dead-time and a result are dropping data. This is a problem for the ucesb unpacker as it will quite working if one of the subsystem stops sending data. (@Nic is this correct?)
>
> This is indeed what I see as whenever we try to run FAIRROOT the tree builder exits immediately."
We have increased the all thresholds excluding aida10 to 0xff. To not trigger on the other FEEs, however better, the DAQ still occasionally runs into dead time and as such fails with making trees.
We have thus elected to turn off AIDA and move out the platform. The conclusion is that we are not able to do this fast timing test with a 200 keV threshold. |
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689
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Fri Jan 10 10:03:43 2025 |
TD | LEC fast comparator threshold too low |
> > >
> > > LEC fast comparator has been set to 0x2 (200keV) which is *very* low and means the fast comparator will be triggering on noise.
> > >
> > > The *minimum* LEC fast comparator setting should be in the range 0x5 - 0xa (500-1000keV).
> > >
> > > I have set the TapeServer to 'no storage' mode to avoid filling the aida-gsi disk with rubbish.
> >
> > Thanks. From the DESPEC elog.gsi.de/despec/Implantation+Stack/18
> >
> > "We have made a trigger from the BGO logic and OR64 of the fast discriminator from AIDA. This was sent as a trigger to the bPlast Exploder.
> >
> > This did not work as the FEE64s of AIDA are running into high dead-time and a result are dropping data. This is a problem for the ucesb unpacker as it will quite working if one of the subsystem stops sending
data. (@Nic is this correct?)
> >
> > This is indeed what I see as whenever we try to run FAIRROOT the tree builder exits immediately."
>
> We have increased the all thresholds excluding aida10 to 0xff. To not trigger on the other FEEs, however better, the DAQ still occasionally runs into dead time and as such fails with making trees.
>
> We have thus elected to turn off AIDA and move out the platform. The conclusion is that we are not able to do this fast timing test with a 200 keV threshold.
Per our discussions in December 2024 this is exactly what would be expected. |
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18
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Thu Jan 24 10:21:26 2019 |
CA, TD, NH, VP | January 24th 2019 |
10.30 AIDA setup and DAQ start complete
writing to file TapeData/NULL/R1
FEE64 Temperatures and Good event statistics ok (attachments 1 and 2)
11.00 results of analyser - shows significant number of timewarps in aida07, and a few in aida01-04
11.24 compared timestamps between mbs and AIDA, agree to 8 digits (attachment 3)
12.49 DAQ and Merger stopped and restarted
Raised slow comparator threshold from 0xa to 0x64
Raised fast comparator threshold (LEC/MEC) from 0xf to 0xff
12.51 Good event statistics: aida08 running at a normal rate
pulser peak (1.8.L) no longer has noise shoulder (attachment 4)
writing to file TapeData/NULL/R2
13.58 stopped writing to file. Pulser frequency increased to 1 kHz
writing to file TapeData/NULL/R3
15.00 file R4 - DAQ startup
17.58 trimmed and re-crimped ground wire on aida08
lowered pulser freq back to 50Hz
reduced slow comparator threshold to 0xa, fast comparator threshold (LEC) to 0xf
good event stats ok, aida08 no longer running hot (attachment 6)
1.8.L and 1.8.W spectra of aida08 (attachment 5)
pulser peak width now at 55.71
FEE64 temperatures ok (attachment 7) |
| Attachment 1: 240119_stats.png
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| Attachment 2: 240119_temp.png
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| Attachment 3: 240119_timestamps.png
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| Attachment 4: 240119_fee8_18L.png
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| Attachment 5: 240119_spectra.png
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| Attachment 6: 1740Statsafter240119.png
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| Attachment 7: 240119_tempafter.png
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17
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Wed Jan 23 17:03:08 2019 |
CA, TD, NH, VP | January 23rd 2019 |
Post White Rabbit update
Attachment 1 - 1.8.W pulser waveform spectra for all FEE64
- pulser signals observed in all FEE64
Attachment 2 - good event statistics - aida08 has significant noise
Attachment 3 - FEE64 temperatures - all ok, but firmware version not displayed
Attachment 4 - 1.8.L pulser peak spectra
- widths:
aida01 - 23.66
aida02 - 19.76
aida03 - 20.43
aida04 - 18.82
aida05 - 20.05
aida06 - 41.04
aida07 - 21.24
aida08 - 205.02 (noisy FEE64)
aida09 - 24.81
aida10 - 22.85
aida11 - 13.98
aida12 - 19.90
Attachment 5 - New Merger statistics
Attachment 6 - Raw data stream |
| Attachment 1: 230119_18W.png
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| Attachment 2: 230119_stats.png
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| Attachment 3: 230119_temp.png
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| Attachment 4: 231019_18L.png
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| Attachment 5: 231019_mergestats.png
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| Attachment 6: 231019_rawdatastream.png
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15
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Wed Jan 23 08:12:01 2019 |
CA, TD, NH, VP | January 22nd 2019 |
Attachment 1 - 1.8.W waveform spectra with pulser signal
Attachment 2 - 1.8.L pulser peak spectra
widths: aida01 - 16.06
aida04 - 20.68
aida05 - 14.03
aida08 - 73.02
aida09 - 669.29
aida11 - 405.35
aida12 - 397.6
Attachment 3 - good event statistics
fast comparator threshold (LEC) at 0xff
FEEs 8,9,11,12 running hot
Attachment 4 - FEE64 temperatures - all ok
System wide checks ok, except aida02 fails ADC calibration
Leak found in seal on cooling pipe, switched power off |
| Attachment 1: 220119_18W.png
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| Attachment 2: 220119_pulserpeaks.png
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| Attachment 3: 220119_stats.png
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| Attachment 4: 220119_Temp.png
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555
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Tue Apr 2 12:36:25 2024 |
JB, CC, NH | Installing FEE64s of DSSSD2 cont. |
Some additional checks
- check 'top hat' electrical isolators are correctly installed at each of the 4x mounting points of the AIDA snout assembly
- check snout is electrically isolated with respect to AIDA support assembly/stand, bPlas PCBs/cabling/ground/drain wires and BB7
- check LK1 installed aida02 or aida04 *and* aida06 or aida08 ( I assume these are the n+n Ohmic FEE64s? )
- check LK3 installed bottom, middle p+n junction FEE64s ( i.e. LK3 installed on 2 of 16 FEE64 adaptor PCBs )
- check FEE64 power cables are paired correctly, e.g. aida02 & aida04, aida01 & aida03 etc. Remember that the numbering of the power cables at the FEE64 PSUs may no longer correspond to which FEE64 is actually connected to that cable
- check test and test - cable daisy chains are removed
- check ground cabling attachment to Lemo 00.250 connectors is tight - they have tendency to loosen with handling
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552
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Wed Mar 27 14:22:35 2024 |
JB, NH | Installing FEE64s of DSSSD2 |
Mounted on frame:
DSSD 1 (Upstream) : 3208-2/3208-5/3208-8
DSSD 2 (Downstream): 3208-3/3208-21/3208-22
Current mapping has been redone for better management.
| AIDA - FEE Mapping |
| DSSSD 1 |
DSSSD2 |
| FEE |
MAC |
FEE |
MAC |
| aida01 |
41:ba:8a |
aida06 |
41:05:15 |
| aida02 |
41:f6:b7 |
aida07 |
41:f6:5a |
| aida03 |
41:d8:21 |
aida08 |
41:d7:cd |
| aida04 |
41:a0:71 |
aida10 |
41:d0:0E |
| aida05 |
41:cf:ac |
aida13 |
41:d8:2b |
| aida09 |
41:ee:10 |
aida14 |
42:0d:15 |
| aida15 |
41:b4:0c |
aida11 |
41:EE:0f |
| aida12 |
41:ba:89 |
aida16 |
41:f6:ed |
Going to try optimising noise now.
DHCP updated
new ASIC settings: 2024Mar27-11.25.32 - 16 FEEs (2,4,6,8 n+n, rest p+n)
New layouts: /home/npg/LayOut/GSI_Triple_S100
New layout.txt
Firmware of aida11 updated from 0xea40704 to 0x3350706
Temps GOOD fig 5
Rates fig 6, 7
Check adapter alignment aida14 and aida16
bPlas left/right cables are not insulated and shorting to the snout
Logs on nnpi1 archived and deleted, start again
All 16 FEEs are showing USB logging connectivity and can be monitored with Pi_Monitor
From waveforms aida08 and aida16 are quite unhappy. The rest don't seem too bad. DSSSD 1 is much quieter than it was before!
White Rabbit Analysis: aida02 has lots of WR error counter, HDMI reseat needed
aida09-12 have no WR timestamp, the cable to the MACB is bad or the MACB is bad.
Not needed to fix right now (for noise testing)
Turn off bPlas
We see the noise drop a lot |
| Attachment 1: Screenshot_2024-03-15_at_14-41-48_Spectrum_Browser_aidas-gsi.png
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| Attachment 2: Screenshot_2024-03-15_at_14-44-59_Statistics_aidas-gsi.png
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| Attachment 3: Screenshot_2024-03-15_at_14-55-07_System_wide_Checks_aidas-gsi.png
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| Attachment 4: Screenshot_2024-03-15_at_14-57-19_Temperature_and_status_scan_aidas-gsi.png
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| Attachment 5: Screenshot_from_2024-03-27_14-51-12.png
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| Attachment 6: Screenshot_from_2024-03-27_14-53-05.png
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| Attachment 7: Screenshot_from_2024-03-27_14-53-56.png
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| Attachment 8: Screenshot_from_2024-03-27_15-31-10.png
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| Attachment 9: Screenshot_from_2024-03-27_15-35-38.png
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| Attachment 10: Screenshot_from_2024-03-27_15-36-13.png
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| Attachment 11: Screenshot_from_2024-03-27_16-14-44.png
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| Attachment 12: Screenshot_from_2024-03-27_16-15-00.png
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| Attachment 13: Screenshot_from_2024-03-27_16-15-27.png
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| Attachment 14: Screenshot_from_2024-03-27_16-15-56.png
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553
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Thu Mar 28 09:18:53 2024 |
TD | Installing FEE64s of DSSSD2 |
Some additional checks
- check 'top hat' electrical isolators are correctly installed at each of the 4x mounting points of the AIDA snout assembly
- check snout is electrically isolated with respect to AIDA support assembly/stand, bPlas PCBs/cabling/ground/drain wires and BB7
- check LK1 installed aida02 or aida04 *and* aida06 or aida08 ( I assume these are the n+n Ohmic FEE64s? )
- check LK3 installed bottom, middle p+n junction FEE64s ( i.e. LK3 installed on 2 of 16 FEE64 adaptor PCBs )
- check FEE64 power cables are paired correctly, e.g. aida02 & aida04, aida01 & aida03 etc. Remember that the numbering of the power cables at the FEE64 PSUs may no longer correspond to which FEE64 is actually connected to that cable
- check test and test - cable daisy chains are removed
- check ground cabling attachment to Lemo 00.250 connectors is tight - they have tendency to loosen with handling
| Quote: |
|
Mounted on frame:
DSSD 1 (Upstream) : 3208-2/3208-5/3208-8
DSSD 2 (Downstream): 3208-3/3208-21/3208-22
Current mapping has been redone for better management.
| AIDA - FEE Mapping |
| DSSSD 1 |
DSSSD2 |
| FEE |
MAC |
FEE |
MAC |
| aida01 |
41:ba:8a |
aida06 |
41:05:15 |
| aida02 |
41:f6:b7 |
aida07 |
41:f6:5a |
| aida03 |
41:d8:21 |
aida08 |
41:d7:cd |
| aida04 |
41:a0:71 |
aida10 |
41:d0:0E |
| aida05 |
41:cf:ac |
aida13 |
41:d8:2b |
| aida09 |
41:ee:10 |
aida14 |
42:0d:15 |
| aida15 |
41:b4:0c |
aida11 |
41:EE:0f |
| aida12 |
41:ba:89 |
aida16 |
41:f6:ed |
Going to try optimising noise now.
DHCP updated
new ASIC settings: 2024Mar27-11.25.32 - 16 FEEs (2,4,6,8 n+n, rest p+n)
New layouts: /home/npg/LayOut/GSI_Triple_S100
New layout.txt
Firmware of aida11 updated from 0xea40704 to 0x3350706
Temps GOOD fig 5
Rates fig 6, 7
Check adapter alignment aida14 and aida16
bPlas left/right cables are not insulated and shorting to the snout
Logs on nnpi1 archived and deleted, start again
All 16 FEEs are showing USB logging connectivity and can be monitored with Pi_Monitor
From waveforms aida08 and aida16 are quite unhappy. The rest don't seem too bad. DSSSD 1 is much quieter than it was before!
White Rabbit Analysis: aida02 has lots of WR error counter, HDMI reseat needed
aida09-12 have no WR timestamp, the cable to the MACB is bad or the MACB is bad.
Not needed to fix right now (for noise testing)
Turn off bPlas
We see the noise drop a lot
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