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ID |
Date |
Author |
Subject |
Text |
 |
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490
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Wed Jun 22 10:09:12 2022 |
PJCS | INFO: FEE64 supply Voltages | Study of the FEE64 power supply distribution
has yielded the following :-
The most sensitive regulator, as |
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514
|
Wed Sep 14 19:07:07 2022 |
PJCS | INFO : Three Merger Statistics explained | There are three Merger statistics that
can be used to better understand how the
data flow through the Merger system is proceeding. |
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300
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Fri May 7 19:47:54 2021 |
PJCS | HowTo mitigate excessive temperature in an FEE64 | After tests in the Daresbury T9 system.
Disabling the waveform ADCs in
an FEE64 which is running with the FPGA over |
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52
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Mon May 20 13:51:45 2019 |
NH | HowTo Verify WR Times | The latest version of MIDAS has a new page
to check the WR timestamp of each FEE.
In AIDA Hardware control click: |
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211
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Wed Mar 31 15:46:09 2021 |
PJCS | HowTo : Synchronize the ASIC clocks. | To Synchronize the FEE64 ASIC clocks to
rise at the same timestamp time use the System
function Synchronise the ASIC clocks |
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209
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Wed Mar 31 12:46:10 2021 |
PJCS | HowTo : Calibrate the LMK3200 clock devices | Here is a document showing how and where
to calibrate the LMK3200 devices that lock
to the system clock and generate the clocks |
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36
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Tue Mar 26 14:58:09 2019 |
NH, VP | How to reset merger | If the merger doesn't show "xfer
Links => Merger" at the top, it is
probably the merger setting has been corrupted |
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63
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Wed Aug 14 14:40:18 2019 |
NH | High Frequency Noise in AIDA | Figures of intense high frequency noise
pickup in AIDA.
Will investigate source in S4. |
|
|
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133
|
Tue Feb 25 09:55:59 2020 |
NH | HV Scope Traces | Looking at the HV bias in a scope to see if
it is the source of noise especially on the
p+n side
|
10x |
|
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672
|
Wed Dec 4 09:57:24 2024 |
TD | HISPEC DESPEC meeting presentation - November 2024 -0 Summary of AIDA performance 2024 | |
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403
|
Sat Mar 5 10:43:45 2022 |
OH, NH | Grounding and noise tests 4th-5th March Summary | Tests performed
After
leaving overnight noticed the pulser was
not fully inserted into aida09
Little |
13x |
|
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392
|
Fri Oct 29 23:00:04 2021 |
NH | Ground cable information | For future refinement of the AIDA ground cables
using copper bus bar or similar:
|
|
|
|
729
|
Tue Oct 28 12:43:38 2025 |
JB, GB, MP, AM | Further setup of tests for 207Bi test | - Ch 2 and 3 of CAEN HV module changed to
negative polarity, Ch 0,1 still with positive
polarity
|
14x |
|
|
730
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Wed Oct 29 08:12:35 2025 |
MP | Further setup for 207Bi test | Inspection of side FEEs (2,6,4,8) and possible
grounding improvements:
- all screws and nuts for copper |
|
|
|
731
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Wed Oct 29 12:56:29 2025 |
TD | Further setup for 207Bi test | Remember that 'ADC calibration'
refers to the setup of the fast serial output
of the AD9222 Octal, 50MSPS, 14 bit ADC which |
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|
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171
|
Thu Mar 4 11:16:13 2021 |
OH | Further cases of possible database issues | During testing for the S452 experiment yesterday
we were running through the steps of a restart.
|
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414
|
Fri Apr 8 08:59:42 2022 |
OH, NH | Friday 8th April | 09:59 Noticed that the right hand ribbon cable
for aida07 was offset vertically by 1. i.e.
Only 1 of the 2 rows of pins in. Unbiassed |
11x |
|
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531
|
Fri Mar 8 16:05:57 2024 |
JB, CC, TD, NH | Friday 8 March | Bias tests of AIDA on individual wafers
and in parallel. Spreadsheet can be found
in attachment 1, and graphic results can |
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|
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299
|
Fri May 7 13:11:22 2021 |
NH | Friday 7th May | 14:11 - Alpha has been running most of morning
Just saw rates in tape spike to 6 MB/s... |
|
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641
|
Fri Jun 7 16:08:37 2024 |
TD | Friday 7 June | 05.01 DSSSD bias & leakage current - attachment
1
|
19x |