 Wed Jan 28 16:19:05 2015, Patrick Coleman-Smith, [How To] Loading new firmware into a FEE64
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Log into the FEE64 module using telnet.
use root
enter => /usr/sbin/flash_unlock /dev/mtd2 |
Thu Jan 29 15:57:01 2015, Patrick Coleman-Smith, [How To] AIDA power supply alteration document 
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I've added the power supply change document.
Please have a look and let me know if it requires further clarification.
I have ordered some plastic "pot twiddlers". |
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Mon Feb 9 11:52:52 2015, Patrick Coleman-Smith, [ How To ] Integrating AIDA with other systems
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| This document details how to integrate AIDA with other systems. |
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Mon Feb 16 09:41:45 2015, Patrick Coleman-Smith, [How To] Set up the Raspberry Pi for PuTTY
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When logged in and before opening PuTTY open a cmdtool window.
cd /dev
sudo chmod 777 /dev/ttyUSB0 |
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Mon Feb 16 12:17:21 2015, Patrick Coleman-Smith, MACB update for 50Mhz external clock
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This version of the MACB has an additional selection at 5 for a ROOT module.
This will operate the Correlation Scalar signals used for RIBF and use the External Clock signal directly for the FEE64 50MHz distribution.
This has been tested at Daresbury with and external clock source and operates successfully with the merger. |
 Tue Feb 17 08:03:32 2015, Patrick Coleman-Smith, [How To] Set up the Raspberry Pi for PuTTY
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Quote:
When logged in and before opening PuTTY open a cmdtool window. |
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Wed Feb 18 11:25:54 2015, Patrick Coleman-Smith, Investigations into removing HV noise
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With the system in T9 and a Keithley Source Meter supplying HV to the detector.
The source meter supplies 200V and measures the current ....
I noticed that the current value was not stable... varying by +/-0.5uA. In conversation with Marcello i learnt that normally much more stable than |
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Mon Mar 9 09:02:03 2015, Patrick Coleman-Smith, Adding Filters to the AIDA PSU.
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| This guide is to help with the filter pcb assembly and installation into the AIDA power supply. |
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Wed Apr 29 10:01:27 2015, Patrick Coleman-Smith, Fast Trigger output fault in FEE64 FPGA logic
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The Fast Trigger output of the FEE64 is formed from the OR of the four OR16 signals ( one from each of the ASICs.
The logic levels of the OR16 signals are active low in the FPGA and so if the are OR'd together then the output is inactive if any one of the ASICs
is inactive. |
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Wed Apr 29 11:34:09 2015, Patrick Coleman-Smith, Fast Trigger timings against Pulser Input and LEC/MEC Fast Comparator threshold setting
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I have tried the latest version ( 26 ) of the FEE64 code and carried out some measurements of the Fast Trigger delay from the Pulser signal ( not the
Pulser Trigger out ) and observed the following.
The pulser gives a centroid of 28217 in the histogram. |
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Thu Apr 30 15:28:25 2015, Patrick Coleman-Smith, High Energy Spectra from LYCCA with pulser
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I have an eight FEE64 system now in place on the LYCCA chamber with a PB-5 pulser going into the adapter cards test input. The test capacitor is 30pF.
I was going to explore the effect of the thresholds on the pulser peak.
I notice that the spectra look like those taken in RIKEN and not a single peak. In the 1GeV range I would interpret this as noise but since this |
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Thu Apr 30 17:43:36 2015, Patrick Coleman-Smith, High Energy Spectra from LYCCA with pulser
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I have an eight FEE64 system now in place on the LYCCA chamber with a PB-5 pulser going into the adapter cards
test input. The test capacitor is 30pF.
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Thu Apr 30 20:21:20 2015, Patrick Coleman-Smith, High Energy Spectra from LYCCA with pulser
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> I have an eight FEE64 system now in place on the LYCCA chamber with a PB-5 pulser going into the adapter cards
> test input. The test capacitor is 30pF.
>
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Wed Jul 1 16:42:39 2015, Patrick Coleman-Smith, Testing Version 8
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I have installed Version 8 of the AidaExec program and FEE_GF_Feb15_6.bin for the VHDL on the system in T9.
On the whole the new firmware operates successfully.
I am now pursuing a few niggles. |
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Thu Jul 16 15:10:34 2015, Patrick Coleman-Smith, [DAQ and VHDL] Changes to the Discriminator Information data item
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| I have attached a document describing the new format of the Discriminator Information data item used in Version 8 |
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Fri May 13 13:24:42 2016, Patrick Coleman-Smith, An idea that might help when everything grinds to a halt
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When using the T9 system and running with too much rate in one FEE64 so the system is unbalanced.
I found a good way to understand this and to be able to operate the controls of the FEE64s was to place the Merger in "Pause" mode.
Then the data is extracted from the busy FEE64 but it can still be controlled. |
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Mon May 23 09:17:55 2016, Patrick Coleman-Smith, Multiplicity Trigger Specification
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| Please read and comment on the attached specification. |
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Mon May 23 17:21:29 2016, Patrick Coleman-Smith, [HowTo] A solution to the problem of no SYNCs
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When starting Aida some FEE64 fail to provide SYNC data , or any data for that matter, on the ASIC data stream.
The problem is that the ASIC Readout is not starting properly and is becoming stuck waiting for an internal
event which will never arrive.
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Tue May 24 08:28:28 2016, Patrick Coleman-Smith, [HowTo] Save power if not using the Waveforms and restart the Waveforms
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The USB controlled power Relays are near their AC fuse operating limit which has caused some Fuse failures.
To reduce the power consumption of each FEE64 it is possible to power down the Waveforms ADCs saving about 20W per FEE64.
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Wed May 25 18:51:54 2016, Patrick Coleman-Smith, [HowTo] Use the Multiplicity Trigger Firmware, V8.18, and update the files
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The attached firmware file, FEE_GF_Feb16_18.bin, should be saved to /MIDAS/Aida and the FlashPgm.csh file edited
to load "FEE_GF_Feb16_18.bin"
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