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Date |
Author |
Subject |
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396
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Wed May 10 19:06:18 2023 |
RSS, TD | V-I test |
To test the detectors, adaptors were installed on the feed through flanges. A negative bias voltage was applied in steps of 10 V from 0 to 150 V. The V-I plots are attached for the four detectors. Three detectors - top right, top left, and bottom left (in the direction of the beam) - are fine. For the bottom right detector (in the direction of the beam), the current was fluctuating and was considerably high (1st test). The adaptors connecting to this detector were removed and checked by applying the bias voltage which showed zero current for voltages ranging from 0 to - 150 V, confirming the adaptors to be fine. They were then exchanged by other adaptors and the V-I test was repeated again (2nd test) with fluctuating and high current values. One of the flanges connecting to this detector was found to be light-tight. These tests were done at an ambient temperature of 21 degrees. Also, we couldn't find the rest of the three SHV to 2x Lemo 00 cables for the detector HV. |
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395
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Tue May 2 15:02:09 2023 |
CB, JM | All detectors and harnesses mounted |
Completed mounting harnesses and detectors.
The strain relief support for the bottom most two detectors on the feedthrough side was not mounted because we could not find enough MACOR parts and mounting flanges. We cannot find them in GSI, possibly they are somewhere not obvious in Edinburgh.
The strain relief on the detectors' side are still being manufactured.
We plan to test the detectors electrically from next week without moving the dolly. DR and OG to find a temporary mounting point for the manifold so that FEEs can be cooled in current configuration. |
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394
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Mon May 1 18:21:18 2023 |
CB, JM | All detectors mounted |
Mounted four detectors on Carme ad well as four cable harnesses.
Cables for new, shorter harnesses appear still too long. Likely the model is not correct somehow.
One feedthrough flange was found to be damaged by an adaptor card. Tried to fix in vain. One pin is missing. Replaced with another. |
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393
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Mon May 1 08:26:09 2023 |
CB, JM | Left hand detectors remounted |
(31 April)
Remounted 3335-12 on top and new 3335-1 on bottom of left hand plate. Used new dog legs and old standoffs.
Dismounted all harnesses and feedthroughs from CARME. Dismounted all blind flanges on right hand side. Also had to dismount bottom SAES feedthrough due to a bolt falling inside.
Remounted feedthough. Remounted left hand detector plate.
Prepared new 3335-11 and 3335-13 on top and bottom of right hand plate. Planning to mount tomorrow.
Also planning to start jacking in detectors to new harnesses.
Not possible to test any detector on the bench due to lack of appropriate multimeter probe. Will have to test with harnesses. |
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392
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Sun Apr 30 10:01:39 2023 |
CB, JM | Left hand detectors unmounted |
(29 April)
Inspected CARME after opening. See attached. Some key takeaways.
- No visible damage to the detectors or the Kapton cables. No visible deposits or dust on the detectors either.
- No damage even to the fragile thermocouple wires
- The strain relief on the top and bottom did nothing. Those on the sides may have helped.
- The split funnels on top fell and fortunately missed the detectors. We should not keep them. Unclear if they feel when moving CARME or during the beamtime but either is too dangerous. We need another solution or we'll have to do without.
- Obvious traces of white dust particles over the chamber. Most likely MACOR.
Jacked out harness for bottom left detector that was not accepting bias. MACOR shavings fell off while jacking out. MACOR connector on side with no pins is clearly damaged. See attached. Should not affect performance.
Tested bias pins - they work. No visible damage to the detector except one bias bond wire has disconnected. Possibly one more nearby. TD thinks this is not enough to explain observed behaviour.
Mounting a DSSD on the plate while it hangs in Carme appears possible but very risky. Dismounted whole left support plate, and right support plate.
Unless a clear fault can be identified for either the bottom left detector or its harnesses, both the detector and the harnesses will be replaced. Plan to remount top left detector with the same harnesses.
Plan to mount two more detectors on the right hand plate. |
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391
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Sat Apr 29 10:12:58 2023 |
CB, JM | CARME opened |
(28 April)
Mounted rails on dolly. The rails don't smoothly connect to those on the Aluminium frame and some thin metal shims were required to get the correct height. A metal support had to be placed above the Delrin pads to support the rails above the gap between frames.
All side feet were mounted but extensive modifications were required to slotted feet due to them not being manufactured to drawing, and to Carme middle section flange width being incorrect (see previous entry).
Removed brakes and started sliding CARME out. The dolly and the aluminium frame came partly separated as the weight of the side feet was shifted on the latter. Strapped them together. No damage.
Kept sliding. Sliding when the carriages passed from one rail to the other was quite hard. The back carriage on the left looking downstream lost a single ball bearing when crossing over. A more sophisticated solution is probably required.
Once Carme was on the dolly, opened it using M8 jacking bolts and lifted away front and middle section.
No obvious damage inside but strain relief did not work as intended. Photos to be uploaded after more detailed inspection on Saturday.
Plan to install right hand side detectors over the weekend. Unclear if bottom left detector is damaged and needs to be replaced. |
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390
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Thu Apr 27 19:43:23 2023 |
CB, JM | Preparing to open |
Removed turbo pump and set aside in a box. Considering switching to the other turbo to avoid degradation due to lack of use.
Installed bellows support and OG devised support to avoid bellows sagging when Carme is split open.
Attempted to install new CARME feet, but there were issues. Feet with slots produced do not match design drawings by PB. Slot is in the wrong side. Furthermore Carme interaction chamber flange thickness is 36 mm vs. 36.5 mm in drawing. DR can modify feet to make them fit tomorrow.
Now just waiting for rails to open CARME. Will arrive tomorrow or on Tuesday, after weekend and Mayday.
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389
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Wed Apr 26 16:49:28 2023 |
CB, JM | CARME dolly mostly built |
Disconnected cables from CARME motors and turbo. The turbo has to go to allow Carme to slide out. Crane may be required to lift because it's in a very hard spot to access.
Dolly mostly built. See attached. Left side doesn't quite fit right by 1-2 mm. Might be okay anyway but will put some shims to avoid any shaking during sliding.
Waiting for the rails to arrive due to GSI procurement issues.
Plan to mount new feet and bellow support tomorrow.
Also plan to split CARME at the smaller flange towards the interaction chamber, after the bellows and before the bellows towards the magnet on the downstream side. |
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388
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Tue Apr 25 13:22:19 2023 |
JM | CARME venting |
CARME venting using nitrogen gas bottle.
Coolant pipes dismounted from the chamber
Feed-through flange for n+n bias flange for bottom detector has a bent pin image attached. Clearer image of bent pin for ERNI connector used for aida03 also attached. All other feed-throughs and adaptor cards appear undamaged. |
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387
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Mon Apr 24 21:24:26 2023 |
JM | Preparation for CARME dismount |
CARME currently in vacuum, pressure ~3E-10 mbar. Chamber to be vented tomorrow afternoon by vacuum division. We have active both pirani and hot cathode gauge to aid.
Equipment removed from the chamber in preparation for dismount of CARME from the ring this week. Equipment removed includes:
- Neg pump cabling
- Heating wire
- FEE electronic units and associated cabling (power, hdmi etc)
- Stainless steel FEE holders
- Red and blue cooling hoses
Attached image shows chamber following equipment removal. Adaptor cards still attached to feed-through flanges. ERNI connnectors examined, all fine except for FEE aida03 which has a bent pin (see attached image). Will dismount adaptor cards to examine further tomorrow. Feed-through flanges will also be examined to check for bent pins following adaptor card removal.
New CARME frame is part constructed and is in the CRYRING area. Requires rails and castors which should arrive this week. The height of the frame will require shortening, to be level with the current frame. This will be looked into further tomorrow. |
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386
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Wed Mar 22 16:33:32 2023 |
TD | NIM WR source |
Test of NIM WR source at Edinburgh
Attachment 1 - NIM WR source
NIM module upper SMA - DSO ch 1
NIM module lower SMA - DSO ch 2
Attachment 2
NO SYNC or CLK signals observed.
Noise observed with NIM bin power ON *and* OFF
Attachment 3
NIM WR source in EG&G Ortec NIM bin
... and with the Digilent Zybo board switched ON!
Attacments 4-7
Trigger ch 2
4, 40, 400 & 4000ns/div
Attachment 8
Trigger ch 1
4ns/div |
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385
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Wed Jan 18 13:32:36 2023 |
PJCS | MACB settings with either Emulator or VETAR |
When using the VITAR connected to the HDMI port of the root MACB the settings for all the MACB in the system 0x3.
This setting takes the Clock and Data line from the input HDMI and outputs it via teh HDMI output ports.
When using the Emulator connected via the SMA connectors on the back of the root MACB then the setting for the root MACB should be 0xD and all others should be 0x3.
Attached is the .jed file for programming the MACB and the .vhd source file to help with understanding of the settings. |
| Attachment 1: macb_apr20.jed
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| Attachment 2: macb_apr20.vhd
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:03:27 03/16/2011
-- Design Name:
-- Module Name: macb_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
-- NOTE all in/out notations are relative to this unit
entity macb_apr20 is
Port (
port1_sp : inout STD_LOGIC_VECTOR (3 downto 0);
port2_sp : inout STD_LOGIC_VECTOR (3 downto 0);
port3_sp : inout STD_LOGIC_VECTOR (3 downto 0);
port4_sp : inout STD_LOGIC_VECTOR (3 downto 0);
layer_sp : inout STD_LOGIC_VECTOR (3 downto 0);
layer_trigger : out std_logic ;
sync_return : in STD_LOGIC_VECTOR (3 downto 1);
selector : in STD_LOGIC_VECTOR (3 downto 0);
sync_select : out STD_LOGIC_vector(1 downto 0 );
clock200_select : out STD_LOGIC_vector( 1 downto 0 ) ;
butis_divide_reset : out std_logic ;
butis_divide_s : out std_logic_vector( 2 downto 0 ) ;
clock_5 : in std_logic ;
sync_5 : in std_logic ;
trigger : in std_logic_vector( 3 downto 0 ) ;
MBS_in : in STD_LOGIC_VECTOR (3 downto 0);
MBS_out : out STD_LOGIC_VECTOR (3 downto 0));
end macb_apr20;
architecture Behavioral of macb_apr20 is
signal port1_spi : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port1_spo : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port1_t : STD_LOGIC_VECTOR (3 downto 0) := ( others => '1' );
signal port2_spi : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port2_spo : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port2_t : STD_LOGIC_VECTOR (3 downto 0) := ( others => '1' );
signal port3_spi : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port3_spo : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port3_t : STD_LOGIC_VECTOR (3 downto 0) := ( others => '1' );
signal port4_spi : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port4_spo : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port4_t : STD_LOGIC_VECTOR (3 downto 0) := ( others => '1' );
signal layer_spi : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal layer_spo : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal layer_t : STD_LOGIC_VECTOR (3 downto 0) := ( others => '1' );
signal seli : integer range 0 to 15 := 0 ;
-- well really
signal MBS_in_n : std_logic_vector( 3 downto 0 ) := "0000" ;
begin
MBS_in_n <= ( not MBS_in);
seli <= conv_integer(not selector) ;
-- MBS signal allocations to sp lines and HDMI pin. This maps to NIM connections
-- 0 : MBS_clock10 SP0 13
-- 1 : MBS_reset SP1 14
-- 2 : MBS_reset_rq SP2 15
-- 3 : MBS_Trigger SP3 16
layer_trigger <= trigger(0) or trigger(1) or trigger(2) or trigger(3) ;
-- divider controls set for pass-through
butis_divide_reset <= '1' ; -- for now don't reset ;
process ( seli , MBS_in_n, port1_spi, port2_spi, port3_spi, port4_spi, layer_spi, sync_return ,sync_5 )
-- note : & => concatenate
begin
case seli is
when 0 => --- Master/ Root / MBS / Internal clock
port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= ( others => '0' ) ;
layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
sync_select <= "00" ; -- select sync from port 1
clock200_select <= "00" ; -- select internal 200 MHz oscillator
MBS_out <= MBS_in_n(3) & MBS_in_n(2) & port1_spi(1) & port1_spi(0) ;
butis_divide_s <= "000" ; -- s2 is 0 for pass,
when 1 => --- Master/ Root / MBS / BuTiS clock and SYNC
port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= ( others => '0' ) ;
layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
sync_select <= "01" ; -- select sync from external using SMA input
clock200_select <= "01" ; -- select external 200 MHz oscillator using SMA input
MBS_out <= MBS_in_n(3) & MBS_in_n(2) & port1_spi(1) & port1_spi(0) ;
butis_divide_s <= "000" ; -- s2 is 0 for pass,
when 2 => --- Master/ Branch / MBS / Next layer clock next layer SYNC
port1_spo <= layer_spi(3) & layer_spi(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= layer_spi(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= layer_spi(3) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= layer_spi(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= '0' & '0' & port1_spi(1) & port1_spi(0) ; -- drive the clock and reset down a layer
layer_t <= "1100" ; -- just drive the bottom two bits to the "next" port
sync_select <= "10" ; -- select sync from next_layer
clock200_select <= "10" ; -- select clock from next layer
MBS_out <= layer_spi(3) & layer_spi(2) & port1_spi(1) & port1_spi(0) ;
butis_divide_s <= "000" ; -- s2 is 0 for pass,
when 3 => --- Slave / Branch / MBS / Next layer clock and sync
port1_spo <= layer_spi(3) & '0' & layer_spi(1) & layer_spi(0);
port1_t <= "0100" ; -- drive clock, reset, trigger only
port2_spo <= layer_spi(3) & '0' & layer_spi(1) & layer_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= layer_spi(3) & '0' & layer_spi(1) & layer_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= layer_spi(3) & '0' & layer_spi(1) & layer_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= '0' & '0' & '0' & '0' ; -- drive nothing
layer_t <= "1111" ; -- just drive nothing down
sync_select <= "10" ; -- select sync from next layer
clock200_select <= "10" ; -- select clock from next layer
MBS_out <= layer_spi ; -- map all the signals for monitoring ?
butis_divide_s <= "000" ; -- s2 is 0 for pass,
when 4 => --- Master/ Root / MBS / BuTiS clock / Internal SYNC / External timestamp reset
port1_spo <= MBS_in_n(3) & '0' & MBS_in_n(1) & '0' ;
port1_t <= "0100" ; -- drive clock, reset, trigger only
port2_spo <= MBS_in_n(3) & '0' & MBS_in_n(1) & '0' ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & MBS_in_n(1) & '0' ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & MBS_in_n(1) & '0' ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= ( others => '0' ) ;
layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
sync_select <= "00" ; -- select sync from port 1
clock200_select <= "01" ; -- select external 50 MHz oscillator using SMA input
MBS_out <= MBS_in_n(3) & MBS_in_n(2) & MBS_in_n(1) & sync_5 ;
butis_divide_s <= "000" ; -- s2 is 0 for pass,
when 5 => --- Master/ Root / MBS / External 50Mhz clock / Internal Sync
port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= ( others => '0' ) ;
layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
sync_select <= "00" ; -- select sync from port 1
clock200_select <= "01" ; -- select external SMA input
MBS_out <= MBS_in_n(3) & MBS_in_n(2) & port1_spi(1) & port1_spi(0) ;
butis_divide_s <= "000" ; -- s2 is 0 for pass through.
when 6 => --- Master/ Root / MBS / External 100Mhz clock / Internal Sync
port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= ( others => '0' ) ;
layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
sync_select <= "00" ; -- select sync from port 1
clock200_select <= "01" ; -- select external SMA input
MBS_out <= MBS_in_n(3) & MBS_in_n(2) & port1_spi(1) & port1_spi(0) ;
butis_divide_s <= "100" ; -- s2 is 1 for external, 00 for /2.
when 7 => --- Fast NIM input for each FEE / Next layer clock next layer SYNC
port1_spo <= MBS_in_n(0) & layer_spi(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(1) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(2) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= '0' & '0' & port1_spi(1) & port1_spi(0) ; -- drive the clock and reset down a layer
layer_t <= "1100" ; -- just drive the bottom two bits to the "next" port
sync_select <= "10" ; -- select sync from next_layer
clock200_select <= "10" ; -- select clock from next layer
MBS_out <= layer_spi(3) & layer_spi(2) & port1_spi(1) & port1_spi(0) ;
butis_divide_s <= "000" ; -- s2 is 0 for pass,
when 8 => --- Fast NIM input from Input 3 for each FEE / Next layer clock next layer SYNC
port1_spo <= MBS_in_n(3) & layer_spi(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= '0' & '0' & port1_spi(1) & port1_spi(0) ; -- drive the clock and reset down a layer
layer_t <= "1100" ; -- just drive the bottom two bits to the "next" port
sync_select <= "10" ; -- select sync from next_layer
clock200_select <= "10" ; -- select clock from next layer
MBS_out <= layer_spi(3) & layer_spi(2) & port1_spi(1) & port1_spi(0) ;
butis_divide_s <= "000" ; -- s2 is 0 for pass,
when 9 => --- Master/ Root / Internal clock / sync_returns to NIM
port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= ( others => '0' ) ;
layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
sync_select <= "00" ; -- select sync from port 1
clock200_select <= "00" ; -- select internal 200 MHz oscillator
MBS_out <= sync_return(3) & sync_return(2) & sync_return(1) & '0' ;
butis_divide_s <= "000" ; -- s2 is 0 for pass,
when 10 => --- Master/ Root / MBS / BuTiS clock /2 and SYNC
port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= "0000" ;
layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
sync_select <= "01" ; -- select sync from external using SMA input
clock200_select <= "01" ; -- select external 200 MHz oscillator using SMA input
MBS_out <= MBS_in_n ; -- for testing NIM I/O
butis_divide_s <= "100" ; -- s2 = 1 and s1,s0 decode to 00=>/2 , 01=>/4, /8 , /16
when 12 => --- Master/ Root / MBS / BuTiS clock /2 and SYNC
port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= ( others => '0' ) ;
layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
sync_select <= "01" ; -- select sync from external using SMA input
clock200_select <= "01" ; -- select external 200 MHz oscillator using SMA input
MBS_out <= MBS_in_n(3) & MBS_in_n(2) & port1_spi(1) & port1_spi(0) ;
butis_divide_s <= "100" ; -- s2 = 1 and s1,s0 decode to 00=>/2 , 01=>/4, /8 , /16
when 13 => --- Master/ Root / MBS / BuTiS clock /4 and SYNC
port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= ( others => '0' ) ;
layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
sync_select <= "01" ; -- select sync from external using SMA input
clock200_select <= "01" ; -- select external 200 MHz oscillator using SMA input
MBS_out <= MBS_in_n(3) & MBS_in_n(2) & port1_spi(1) & port1_spi(0) ;
butis_divide_s <= "101" ; -- s2 = 1 and s1,s0 decode to 01=>/4
when 14 => --- Master/ Root / MBS / BuTiS clock /8 and SYNC
port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
... 161 more lines ...
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384
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Thu Dec 8 14:41:19 2022 |
PJCS | Results of tests on AIDA PSU in DL T9 |
We opened one up and soldered a co-ax cable to one of the +6v power contacts at the output of the filter board.
Connecting this to a 'scope we observed a level of +/- 5mv noise with no FEE connected.
Connecting one FEE made little difference.
Re-connected the FEE to the power supply in the cabinet and wired a co-ax to a spare FEE power plug.
Ran the system with two FEEs on the bench top and two in the cabinet. The benchtop FEEs were connected to the NIM bin in the cabinet with copper braid.
Using a PB4 in the NIM bin and my test input cards on the FEE mezzanine connector, the following readings were taken using the 'integrate' function in the spectrum browser.
Shaping 8us, negative pulse.
aida02, ASIC1, ch0 Peak width => 16.58 channels ( full 16 bit spectra )
aida03, ASIC1, ch0 Peak width => 18.48 channels ( full 16 bit spectra )
aida04, ASIC1, ch0 Peak width => 18.05 channels ( full 16 bit spectra )
These could be better but the output of the PB4 was not perfect. I think ASIC 1 Ch0 is normally the worst on the mezzanine.
Attachments 1 to 6 are the waveforms and some zoomed in.
The co-ax from the power supply was connected to a 'scope and showed a noise level of +/-50mv.
Fourier analysis of this noise showed two peaks 109kHz and 218kHz. ( Attachments 7 & 8 ) |
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383
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Thu Dec 1 08:56:59 2022 |
AR TD | Thursday 1 December |
Photos of noise observed at each of the AIDA PSU outputs by digital oscillscope.
DAQ GOing with waveforms enabled.
Connection from AIDA PSU to scope by DMM test probes, twisted cabling, 3mm jack plug/BNC adaptor.
Attachment 1,2,3 = +5V
Attatchment 4 = -6V
Attatchment 5 = +7V
Attatchment 6 shows test setup
Repeat above test with *all* cables from AIDA PSU to FEE64s disconnected, i.e. no AIDA PSU load.
Attachment 7,8,9 = +5V
Attatchment 10 = -6V
Attatchment 11 = +7V |
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382
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Wed Nov 30 08:52:59 2022 |
AR TD | Wednesday 30 November |
9:40
DSSD bias and leakage current values:
-99.99 V
-13.0960 uA
Pulsar peak widths (ch FWHM)
aida01 ~ 97
aida02 ~ 103
aida03 ~ 134
aida04 ~ 131
aida05 ~ 22
Pretty similar to what was found yesterday
15.30
Per Elog 375
Measured FEE64 voltages are as follows
@ISOL 4 AIDA PSU @FEE64 aida05 nominal
(top-botttom) (right-left)
+6.05V +5.26V +5V
+6.05V +5.26V +5V
+6.05V +5.26V +5V
-6.49V -6.26V -6V
+7.78V +7.46V +7V
Adjusted PowerStax PSU voltage pots of AIDA PSU ISOL 4
@ISOL 4 AIDA PSU @FEE64 aida05 nominal
(top-botttom) (right-left)
+5.79V +4.99V +5V
+5.79V +4.99V +5V
+5.79V +4.99V +5V
-6.23V -6.00V -6V
+7.32V +7.00V +7V
Attatchment 1-12 = BEFORE change
Attatchment 13+ = AFTER change
Pulsar peak widths (ch FWHM) AFTER CHANGE
aida01 ~ 100
aida02 ~ 96
aida03 ~ 130
aida04 ~ 130
aida05 ~ 22 |
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381
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Tue Nov 29 14:37:56 2022 |
AR TD | Tuesday 29 November |
16:20
DSSD bias and leakage current values:
-99.99 V
-13.2535 uA
Pulsar peak widths (ch FWHM)
aida01 ~ 100
aida02 ~ 103
aida03 ~ 128
aida04 ~ 133
aida05 ~ 22
Pretty similar to what was found in august https://elog.ph.ed.ac.uk/CARME/377
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380
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Mon Nov 28 13:14:33 2022 |
AR TD | Monday 28 November |
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379
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Mon Oct 3 16:03:33 2022 |
OH, CB | TTT14 Photos |
Photos of the new TTT14 DSSD delivered to GSI.
Photos of detectors are broken up by photos of SN on box
To big to put on elog. Have uploaded to /Disk/ds-sopa-group/np/GSI/CARME/TTT14_Photos.zip and will change permissions to 777 |
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378
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Sun Aug 14 06:50:58 2022 |
TD, JM | Sunday 14 August |
07.51 DAQ continues files 22Feb/R97
ASIC settings 2022Jan31-11-52-00
slow comparator 0x64
EG&G Ortec 448 Pulser OFF
All system wide checks OK
Attachment 1 - ADC data item stats
Attachment 2 - FEE64 temps OK
Attachments 3 & 4, 8 & 9 - per FEE64 1.8.W spectra 20us FSR and 200us FSR
Attachments 5 & 6 - per FEE64 1.8.L spectra
Attachment 7 - per FEE64 stat spectra
Leakage current remains 8.36 uA, 100V.
Bias power OFF, SIP ion pump power back ON. NIM crate powered off. Motors pi and nnrpi1 still on for remote access.
Compressed air off, water off. Fee relay power off and power cable disconnected. Motors box off. Safety pin for motors reinserted.
Checked cable harnesses at cryring. 2 good short sections found and left with boxes in cryring. 2 damaged long sections (bad pin and broken ceramic) taken to repair in
Edinburgh. |
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377
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Sat Aug 13 10:23:59 2022 |
JM, TD | Noise tests pt3 and pulser walk |
Waveforms and discriminator ON. Pulser re-connected to all fees via daisy chain. V=100v, I=8.36uA
Pulser peak widths (ch FWHM)
aida01 ~ 109
aida02 ~ 98
aida05 ~ 24
aida03 ~ 118
aida04 ~ 136
Attachments 2, 3 & 4 1.8.W spectra, 20us FSR
Attachment 5 FEE64 temps OK
Attachment 6 per FEE64 ADC data item rates OK
Attachment 7 per FEE64 rate spectra
Merger reset following procedure from https://elog.ph.ed.ac.uk/DESPEC/36. Keywords for future elog search NetVar, xfer links
Pulser walkthrough R94
EG&G Ortec 448 Pulser settings
Amplitudes 90,000 - 10,000 @ 10,000 step
Attenuators x5 IN
t_r 50ns tau_d 50us
polarity + (- polarity via Cooknell SA1)
Frequency int relay
Motors box turned ON, motors pi ON, dlink network connector ON. Motors box, pi and dlink all in 19 inch rack but power supply is from a uk mains extender daisy chained to vacuum mains extender. 19 inch rack power supply remains on clean line.
Pulser peak widths (ch FWHM)
aida01 ~ 105
aida02 ~ 98
aida05 ~ 23
aida03 ~ 132
aida04 ~ 144
See attachments 8 & 9
Detectors moved in by pnuematic only. Leakage current increased to 9.6 uA (same as leakage current during bias ramping)
Pulser Walk R95
Pulser settings as above
See attachments 10 & 11
Detectors moved back out . Motors box, pi and dlink still turned ON. Leakage current to 8.36 uA
Pulser Walk R96
Pulser settings as above
See attachments 1 & 12
Jumper removed from nn bias fee adaptor board (aida04). No jumpers on any adaptor boards now. V=100V, I=8.36uA
See attachments 14 & 15 - 1.8.W spectra 20us FSR
Pulser on 90,000 x5 attenuate
aida01 ~ 123, centroid ~14691
aida02 ~ 106, centroid ~ 15038
aida05 ~ 23, centroid ~ 14414
aida03 ~ 125, centroid ~ 50838
aida04 ~ 127, centroid ~ 51754
Jumper reinstalled on aida04 nn bias. Note only link 1, link2 inaccesible with fee inserted into ERNI. See attachment 13
aida01 ~ 123, centroid ~14688
aida02 ~ 114, centroid ~ 15034
aida05 ~ 23, centroid ~ 14411
aida03 ~ 118, centroid ~ 50854
aida04 ~ 135, centroid ~ 51697
Pulser off. Background run to be left overnight started 14:24 R97. V=100v, I=8.36 uA. |
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