| ID |
Date |
Author |
Subject |
|
522
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Thu Oct 12 14:01:43 2023 |
TD | MSL type BB18 24cm x 8cm DSSSD test - update |
DSSSD MSL type BB18 24cm x 8cm 3208-3/3208-21/3208-22
FEE64 configuration see https://elog.ph.ed.ac.uk/AIDA/872 attachment 2
Bias -150V -6.590uA ambient temperature +24.7 deg C d.p. +13.7 deg C RH 50.3%
BNC PB-5
amplitude 10.0V
attenuation x10
decay time 1ms
tail pulse
frequency 25Hz
PB-5 output direct to p+n junction side FEE64 aida01 or aida12, or n+n Ohmic side FEE64 aida02
aida01 1.8.L pulser peak width 61 ch FWHM ~ 46keV FWHM => 5s threshold 98keV
aida12 1.8.L pulser peak width 56 ch FWHM ~ 42keV FWHM => 5s threshold 89keV
aida02 1.8.L pulser peak width 102 ch FWHM ~ 77keV FWHM => 5s threshold 163keV
slow comparator 0xa 100keV ( all p+n junction FEE64s )
0xf 150keV ( all n+n Ohmic FEE64s )
per FEE64 Rate spectra - attachment 1
p+n FEE64s ( aida010, aida01, aida09, aida12, aida03, aida11 ) rates dominated by hot channels, other channels typically <1Hz ( 25Hz pulser to aida12 )
n+n FEE64s ( aida02, aida04 ) rates ~ 10-20Hz/channel
Note aida06 and aida08 are not connected to anything and should be ignored
ADC data item stats - attachment 2
For further information see https://elog.ph.ed.ac.uk/AIDA/906 and https://elog.ph.ed.ac.uk/AIDA/907
To Do
- repair/replace Honeywell HSS-DPS dew point sensor
USB-controlled ac mains relay interlock currently overrriden
do NOT operate AIDA unattended
- aida04 asic #1 u/s - replace ASIC mezzanine
- electrically isolated test signal distribution box req'd
- aida10 asic #4
v. high rates observed and large signal transients
cause unclear ... ASIC/adaptor PCB/cabling/Si wafer ?
- extended background alpha run to check all DSSSD bond wires
pulser OFF
slow comparator 0x64
- bPlas + 2x triple DSSSD + bPlas stack assembly and test
- all up, in beam test |
| Attachment 1: Screenshot_from_2023-10-12_15-13-30.png
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| Attachment 2: Screenshot_from_2023-10-12_15-17-05.png
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521
|
Sun Oct 1 11:47:07 2023 |
TD | S4 cooling water |
The photographs show the cooling water controls and temperature/pressure gauges outside S4 and the connections used by AIDA within S4. |
| Attachment 1: 1000007356.jpg
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| Attachment 2: 1000007355.jpg
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|
520
|
Thu Aug 31 15:24:56 2023 |
NH | New AIDA MBS PC |
The AIDA MBS FDR will be x86l-119 from now on, not x86l-94
the MBS relay and startup scripts will be changed for this |
|
519
|
Mon Aug 28 12:47:56 2023 |
NH | Power Failure 24.08.2023 |
There was a power failure in the morning of 24.08.2023 in the Rhein-Main area affecting GSI
The Aida workstation (aida-3) has been restarted, it is unknown if the Pis in S4 rebooted as well (there is a UPS)
29.8.23 TD Both RPi systems rebooted four days ago. |
|
518
|
Sun Jul 16 09:32:57 2023 |
TD | Firefox browser proxy setting change |
Firefox browser proxy setting changed to 'Auto-detect proxy settings for this network' ( Firefox -> Edit -> Settings -> Network Settings -> Settings ) |
|
517
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Wed Jan 18 13:40:33 2023 |
PJCS TD | MACB settings with either Emulator or VITAR |
When using the VETAR connected to the HDMI port of the root MACB the settings for all the MACB in the system 0x3.
This setting takes the Clock and Data line from the input HDMI and outputs it via teh HDMI output ports.
When using the Emulator connected via the SMA connectors on the back of the root MACB then the setting for the root MACB should be 0xD and all others should be 0x3.
Attached is the .jed file for programming the MACB and the .vhd source file to help with understanding of the settings. |
| Attachment 1: macb_apr20.jed
|
| Attachment 2: macb_apr20.vhd
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:03:27 03/16/2011
-- Design Name:
-- Module Name: macb_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
-- NOTE all in/out notations are relative to this unit
entity macb_apr20 is
Port (
port1_sp : inout STD_LOGIC_VECTOR (3 downto 0);
port2_sp : inout STD_LOGIC_VECTOR (3 downto 0);
port3_sp : inout STD_LOGIC_VECTOR (3 downto 0);
port4_sp : inout STD_LOGIC_VECTOR (3 downto 0);
layer_sp : inout STD_LOGIC_VECTOR (3 downto 0);
layer_trigger : out std_logic ;
sync_return : in STD_LOGIC_VECTOR (3 downto 1);
selector : in STD_LOGIC_VECTOR (3 downto 0);
sync_select : out STD_LOGIC_vector(1 downto 0 );
clock200_select : out STD_LOGIC_vector( 1 downto 0 ) ;
butis_divide_reset : out std_logic ;
butis_divide_s : out std_logic_vector( 2 downto 0 ) ;
clock_5 : in std_logic ;
sync_5 : in std_logic ;
trigger : in std_logic_vector( 3 downto 0 ) ;
MBS_in : in STD_LOGIC_VECTOR (3 downto 0);
MBS_out : out STD_LOGIC_VECTOR (3 downto 0));
end macb_apr20;
architecture Behavioral of macb_apr20 is
signal port1_spi : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port1_spo : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port1_t : STD_LOGIC_VECTOR (3 downto 0) := ( others => '1' );
signal port2_spi : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port2_spo : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port2_t : STD_LOGIC_VECTOR (3 downto 0) := ( others => '1' );
signal port3_spi : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port3_spo : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port3_t : STD_LOGIC_VECTOR (3 downto 0) := ( others => '1' );
signal port4_spi : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port4_spo : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port4_t : STD_LOGIC_VECTOR (3 downto 0) := ( others => '1' );
signal layer_spi : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal layer_spo : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal layer_t : STD_LOGIC_VECTOR (3 downto 0) := ( others => '1' );
signal seli : integer range 0 to 15 := 0 ;
-- well really
signal MBS_in_n : std_logic_vector( 3 downto 0 ) := "0000" ;
begin
MBS_in_n <= ( not MBS_in);
seli <= conv_integer(not selector) ;
-- MBS signal allocations to sp lines and HDMI pin. This maps to NIM connections
-- 0 : MBS_clock10 SP0 13
-- 1 : MBS_reset SP1 14
-- 2 : MBS_reset_rq SP2 15
-- 3 : MBS_Trigger SP3 16
layer_trigger <= trigger(0) or trigger(1) or trigger(2) or trigger(3) ;
-- divider controls set for pass-through
butis_divide_reset <= '1' ; -- for now don't reset ;
process ( seli , MBS_in_n, port1_spi, port2_spi, port3_spi, port4_spi, layer_spi, sync_return ,sync_5 )
-- note : & => concatenate
begin
case seli is
when 0 => --- Master/ Root / MBS / Internal clock
port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= ( others => '0' ) ;
layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
sync_select <= "00" ; -- select sync from port 1
clock200_select <= "00" ; -- select internal 200 MHz oscillator
MBS_out <= MBS_in_n(3) & MBS_in_n(2) & port1_spi(1) & port1_spi(0) ;
butis_divide_s <= "000" ; -- s2 is 0 for pass,
when 1 => --- Master/ Root / MBS / BuTiS clock and SYNC
port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= ( others => '0' ) ;
layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
sync_select <= "01" ; -- select sync from external using SMA input
clock200_select <= "01" ; -- select external 200 MHz oscillator using SMA input
MBS_out <= MBS_in_n(3) & MBS_in_n(2) & port1_spi(1) & port1_spi(0) ;
butis_divide_s <= "000" ; -- s2 is 0 for pass,
when 2 => --- Master/ Branch / MBS / Next layer clock next layer SYNC
port1_spo <= layer_spi(3) & layer_spi(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= layer_spi(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= layer_spi(3) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= layer_spi(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= '0' & '0' & port1_spi(1) & port1_spi(0) ; -- drive the clock and reset down a layer
layer_t <= "1100" ; -- just drive the bottom two bits to the "next" port
sync_select <= "10" ; -- select sync from next_layer
clock200_select <= "10" ; -- select clock from next layer
MBS_out <= layer_spi(3) & layer_spi(2) & port1_spi(1) & port1_spi(0) ;
butis_divide_s <= "000" ; -- s2 is 0 for pass,
when 3 => --- Slave / Branch / MBS / Next layer clock and sync
port1_spo <= layer_spi(3) & '0' & layer_spi(1) & layer_spi(0);
port1_t <= "0100" ; -- drive clock, reset, trigger only
port2_spo <= layer_spi(3) & '0' & layer_spi(1) & layer_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= layer_spi(3) & '0' & layer_spi(1) & layer_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= layer_spi(3) & '0' & layer_spi(1) & layer_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= '0' & '0' & '0' & '0' ; -- drive nothing
layer_t <= "1111" ; -- just drive nothing down
sync_select <= "10" ; -- select sync from next layer
clock200_select <= "10" ; -- select clock from next layer
MBS_out <= layer_spi ; -- map all the signals for monitoring ?
butis_divide_s <= "000" ; -- s2 is 0 for pass,
when 4 => --- Master/ Root / MBS / BuTiS clock / Internal SYNC / External timestamp reset
port1_spo <= MBS_in_n(3) & '0' & MBS_in_n(1) & '0' ;
port1_t <= "0100" ; -- drive clock, reset, trigger only
port2_spo <= MBS_in_n(3) & '0' & MBS_in_n(1) & '0' ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & MBS_in_n(1) & '0' ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & MBS_in_n(1) & '0' ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= ( others => '0' ) ;
layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
sync_select <= "00" ; -- select sync from port 1
clock200_select <= "01" ; -- select external 50 MHz oscillator using SMA input
MBS_out <= MBS_in_n(3) & MBS_in_n(2) & MBS_in_n(1) & sync_5 ;
butis_divide_s <= "000" ; -- s2 is 0 for pass,
when 5 => --- Master/ Root / MBS / External 50Mhz clock / Internal Sync
port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= ( others => '0' ) ;
layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
sync_select <= "00" ; -- select sync from port 1
clock200_select <= "01" ; -- select external SMA input
MBS_out <= MBS_in_n(3) & MBS_in_n(2) & port1_spi(1) & port1_spi(0) ;
butis_divide_s <= "000" ; -- s2 is 0 for pass through.
when 6 => --- Master/ Root / MBS / External 100Mhz clock / Internal Sync
port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= ( others => '0' ) ;
layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
sync_select <= "00" ; -- select sync from port 1
clock200_select <= "01" ; -- select external SMA input
MBS_out <= MBS_in_n(3) & MBS_in_n(2) & port1_spi(1) & port1_spi(0) ;
butis_divide_s <= "100" ; -- s2 is 1 for external, 00 for /2.
when 7 => --- Fast NIM input for each FEE / Next layer clock next layer SYNC
port1_spo <= MBS_in_n(0) & layer_spi(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(1) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(2) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= '0' & '0' & port1_spi(1) & port1_spi(0) ; -- drive the clock and reset down a layer
layer_t <= "1100" ; -- just drive the bottom two bits to the "next" port
sync_select <= "10" ; -- select sync from next_layer
clock200_select <= "10" ; -- select clock from next layer
MBS_out <= layer_spi(3) & layer_spi(2) & port1_spi(1) & port1_spi(0) ;
butis_divide_s <= "000" ; -- s2 is 0 for pass,
when 8 => --- Fast NIM input from Input 3 for each FEE / Next layer clock next layer SYNC
port1_spo <= MBS_in_n(3) & layer_spi(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= '0' & '0' & port1_spi(1) & port1_spi(0) ; -- drive the clock and reset down a layer
layer_t <= "1100" ; -- just drive the bottom two bits to the "next" port
sync_select <= "10" ; -- select sync from next_layer
clock200_select <= "10" ; -- select clock from next layer
MBS_out <= layer_spi(3) & layer_spi(2) & port1_spi(1) & port1_spi(0) ;
butis_divide_s <= "000" ; -- s2 is 0 for pass,
when 9 => --- Master/ Root / Internal clock / sync_returns to NIM
port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= ( others => '0' ) ;
layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
sync_select <= "00" ; -- select sync from port 1
clock200_select <= "00" ; -- select internal 200 MHz oscillator
MBS_out <= sync_return(3) & sync_return(2) & sync_return(1) & '0' ;
butis_divide_s <= "000" ; -- s2 is 0 for pass,
when 10 => --- Master/ Root / MBS / BuTiS clock /2 and SYNC
port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= "0000" ;
layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
sync_select <= "01" ; -- select sync from external using SMA input
clock200_select <= "01" ; -- select external 200 MHz oscillator using SMA input
MBS_out <= MBS_in_n ; -- for testing NIM I/O
butis_divide_s <= "100" ; -- s2 = 1 and s1,s0 decode to 00=>/2 , 01=>/4, /8 , /16
when 12 => --- Master/ Root / MBS / BuTiS clock /2 and SYNC
port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= ( others => '0' ) ;
layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
sync_select <= "01" ; -- select sync from external using SMA input
clock200_select <= "01" ; -- select external 200 MHz oscillator using SMA input
MBS_out <= MBS_in_n(3) & MBS_in_n(2) & port1_spi(1) & port1_spi(0) ;
butis_divide_s <= "100" ; -- s2 = 1 and s1,s0 decode to 00=>/2 , 01=>/4, /8 , /16
when 13 => --- Master/ Root / MBS / BuTiS clock /4 and SYNC
port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port3_t <= "0100" ; -- drive clock, reset, trigger only
port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port4_t <= "0100" ; -- drive clock, reset, trigger only
layer_spo <= ( others => '0' ) ;
layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
sync_select <= "01" ; -- select sync from external using SMA input
clock200_select <= "01" ; -- select external 200 MHz oscillator using SMA input
MBS_out <= MBS_in_n(3) & MBS_in_n(2) & port1_spi(1) & port1_spi(0) ;
butis_divide_s <= "101" ; -- s2 = 1 and s1,s0 decode to 01=>/4
when 14 => --- Master/ Root / MBS / BuTiS clock /8 and SYNC
port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
port1_t <= "0011" ; -- drive trigger and reset request only
port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
port2_t <= "0100" ; -- drive clock, reset, trigger only
port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
... 161 more lines ...
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| Attachment 3: zybo.jpg
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| Attachment 4: MACB.jpg
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516
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Fri Dec 16 14:02:12 2022 |
NH | AIDA System off for christmas break |
The AIDA NIM crate, pis and workstation have been powered off for the Christmas break and will not be accessible |
|
515
|
Thu Oct 6 16:51:49 2022 |
NH | Oscilloscope analysis |
Investigating AIDA noise with a TA041 differential probe and oscilloscope
AC Mains (DESPEC platform AC, L-N)
Probe attentuation = 1:100
Fig 1: Main AC waveform [X: 5ms/div, Y: 100 V/div]
Fig 2: Zoomed in at peak (20 V FSR, any less and the waveform clipped) [X: 10us/div, Y: 20V/div]
Fig 3: Longer time base and FFT of 0-5 MHz. No significant frequency harmonics noticed [X: 5ms/div, Y:20 V, FFT X: 500 kHz/div, Y: 10 dBm/div]
No significant noise or distortion present, fully within any AC specification.
Note that at the moment there is almost no load on AC
Equipment on on DESPEC rack: AIDA NIM, AIDA Raspberry Pis, bPlas PC (+ WR) + 2x DESPEC NIM crates
No autofill, VME crate or detectors
All big machines at GSI (SIS, FRS) off (suspect pumps are on)
Ion catcher not on (I think under repair)
-
FEE PSU studies
Probe connected to 5V exposed power pin on FEE64 (+v) and to grounding crimp on FEE64 (-v)
No adapter board connected
Attentuation = 1:10
Fig 4: FFT when FEEs are *off* - essentially probe+scope noise [X: 5ms/div, Y: 100 mV/div, FFT: X: 500 kHz/div, Y: 10 dBm/div]
Fig 5: FFT when FEEs are *on* - notice 1.4 MHz peak in FFT, also seen on ADC waveform readout before (fig 6) [X: 5ms/div, Y: 100 mV/div, FFT: X: 500 kHz/div, Y: 10 dBm/div]
Fig 7: 500 ns/div 5V output on FEE, single FEE on the PSU [X: 500 ns/div, Y: 100 mV/div]
Note average max voltage is 5.31 V (power on) and ~ 70 mV "peak to peak" -might be from probe/scope?
Also see voltage changes with FEE power draw:
Power on : 5.45 V (different scale to above)
SETUP ran : 5.51 V
FADCs off : 5.86 V
ACQ Go: : Unchanged; ASIC threshold 0xa: Unchanged
Also check situation on a fully loaded PSU (8 fees connected and powered on)
Power on: 5.29 V (fig 8)
SETUP ran: 5.36 V (fig 9)
FADCs off: 5.64 V (fig 10)
All X: 500 ns/div, Y: 100 mV/div
Both cases observe voltage rises as current draw drops (as expected for voltage drop along a cable)
Noise on 'scope seems to get slightly worse with reduced current (and higher voltage)
No sign of strong 100 kHz noise as seen in ADC traces beforehand
Todo:
- Check -6V and 7V rails
- Check 5V and noise when front-end card is added and pulser/HV connected
- Check between two FEE64 grounds
- Check direct out of PSU vs ground to see if 1.4 MHz appears on PSU side or FEE64 side
-
11.10.22 Updates
Attachement 11 - 5V PSU on upper PSU with no FEEs attached whatsoever. No 1.4 MHz (on FFT) but clear low frequency beats from switching - presumably low/no load behaviour
Attachement 12 - 5V PSU on aida12 with 8 FEEs on PSU. Longer time base to allow lower frequencies in FFT. 1.4 MHz switching spikes visible but nothing around 100 kHz region
Attachments 13-16: 5V PSU on aida12 at 20 mV/div vertical and 1, 0.5, 2, 5 us/div horizontal respectively
12.10.22 Updates
Attachment 17: -6V PSU on aida12 with 8 FEEs on PSU. 2 us/div timebase. 20 mV/div amplitude
Attachment 18: 10 ms timebase and FFT
Average voltage: -6.21 V
Attachment 19: 7V PSU on aida12 with 8 FEEs on PSU. 2 us/div timebase. 20 mV/div amplitude
Attachment 18: 10 ms timebase and FFT
Average voltage: 7.46V
Measurement between AIDA12 ground and Reference ground/copper bar
+ve (red probe) attached to copper bar at ground point (not strong connection at present)
-ve (black probe) attached to ground crimp on aida12 (connected to cooling plate)
aida12 no adapter board connected: connections are PSU, Ethernet, HDMI and TTY only
Attachment 21: 5 us/div 100 mv/div waveform, big oscillations present. Not seen before FEEs turned on (8 FEES, 1-7+12)
Attachment 22: 10 ms/div for FFT, sharp peak at exactly 100 kHz observed...
Attachment 23: Between 5V PSU (+ve) and 19" rack (-ve) with no FEEs connected to PSU
See strong 100 kHz oscillations too, note that voltage isn't 5V as PSU is floating w.r.t. ground
Looks to be common mode noise (on both 5V and Return of PSU)
Attachment 24: Same as 21 but using thick crocodile clips on probe to ground and aida12. Noise is attenuated but still present |
| Attachment 1: SCRN0086.PNG
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514
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Wed Sep 14 19:07:07 2022 |
PJCS | INFO : Three Merger Statistics explained |
There are three Merger statistics that can be used to better understand how the data flow through the Merger system is proceeding.
Two are from the Link task and one is from the Merger.They are all "No data buffers avaliable" with #1, #2, #3 at the end.
#1: This is incremented when the Link task has a data item to put in the queue for the Merge process but there is no room.
#2: This is incremented when the Link task has found no room in the queue for the Merge process ( #1 ) , waited , tried again and failed.
#3: This the other end of the queue. When the Merge task requests a data item from a Link task queue and there is nothing available.
|
|
513
|
Thu Sep 8 12:37:18 2022 |
NH | Proxy Port Changed |
The proxy in Firefox, Yum and AnyDesk has been changed as the old wasn't working
proxy.gsi.de port 3128 is now in use |
|
512
|
Thu Sep 8 12:31:25 2022 |
NH | Retrying AIDA DataAcq v10 |
Startup AIDA with ribbon cable connected to aida03 and aida07 for noise
Setup and run with waveforms enabled. Discriminators ADC power etc as default
Try to push above 200k as this is where we saw issues before... lowering threshold to 0x3 pushes rates to
aida03 - 320k
aida07 - 254k
Startup merger and observe rates
aida03 - 224k
aida07 - 213k
Rate drop observed as before.
Now update aidacommon to point to AidaExecV10 and powercycle FEEs
Rates again with 0x3
aida03 - 315k
aida07 - 252k
Restart with data transfer ON
aida03 - 317k
aida07 - 262k
No errors in merger terminal or "Merge time errors" statistic
Will keep running |
| Attachment 1: AnyDeskMSI_2022-09-08_13-35-50.png
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| Attachment 2: AnyDeskMSI_2022-09-08_13-35-58.png
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| Attachment 3: AnyDeskMSI_2022-09-08_13-36-02.png
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|
511
|
Tue Aug 30 13:48:32 2022 |
NH | AIDA Single Switch Configuration |
The second switch was moved back to CARME so AIDA has been configured back to using a single switch
aida02/aida04/aida06/aida08 updated back to first switch as per https://elog.ph.ed.ac.uk/DESPEC/433
Additionally a ribbon cable is attached to aida01 and aida05 to introduce some noise into the system |
|
510
|
Tue Jul 5 08:53:20 2022 |
TD | To Do |
In no particular order
1) CAEN 83xx series NIM bin (Ortec 533A output noise issue)
observe +/- 6V, 12V, 24V lines with/without load
try new CAEN NIM bin and/or NIM bin of different type
2) Measure actual voltages at FEE64 power connector input
OH suggests fab of power adaptor for safe observation - contact EW
3) rev B adaptor PCB
invert 125 way ERNI - check for mech conflicts
paired HV input (avoid Lemo-00 T pieces)
consider isolating test/HV Lemo-00 shells from PCB ground (loop elimination)
straight jumpers
shrouded Samtec headers - consider mech issues/consequences of using eject clips too
re-visit HV filtering & separate trace ground
4) isolation transformer
as practical matter may be necessary to operate all platform from isolation transformer
consider hire of appropriate unit
need method to measure isolation - will require permit to work or equiv
5) investigate S4 area ac mains
NH discussing with GSI electricians
6) Systematic measurement of AIDA PSU noise
Spec linear AIDA FEE64 PSU
7) Redesign of snout
Return to 1mm welded box Al for lower stage of snout for added rigidity
8) Revisit calculation of cable lengths. Particularly for the triple
9)
|
|
509
|
Wed Jun 29 10:48:26 2022 |
NH, OH | AIDA Dismounted |
All detectors removed from single and triple AIDA snouts
Empty snouts *and* DSSDs (in boxes) stored in NH office |
|
508
|
Tue Jun 28 10:11:35 2022 |
OH, NH | MIDAS Data Aq V10 |
11:11 Rebooted FEEs and changed aidacommon in /MIDAS/linux-ppc_4xx/startup to point to the new V10 DataAq that Patrick produced
When using V9 the Merger statistics reported WR items at twice the rate of ADC data items.
i.e for ever data item we were sending and info code 4 and info code 5 item sending 192 bits of data vs 64 for just the data word
This was causing significant deadtime when FEEs were running in the range of around 200kHz. These WR items were not reported by the MIDAS Acquisition server but were in the Merger statistics
Patrick has produced V10 which removes these.
When running V10 we can confirm in the Merger statistics that this rate is no longer determined by the ADC data rate and instead controlled via Sync Rollover Target in GSI WhiteRabbit Control.
WR items for 0xE - attachment 1
WR items for 0x7 - attachment 2
However we see in the NewMerger terminal the message shown in attachment 3 frequently.
Also we note that the merger time error counter is also going up.
Our thoughts for this are we have a rollover issue (Is the merger expecting the rollover of the LSB to be one value when the MSB is updated but MIDAS is happening on another?)
Are we having dead time issues which is causing time warps?
Does each buffer from the MIDAS Data Acq start with a full WR timestamp?
aidacommon has been changed back to point to V9 to not cause issues when we run the DAQ and forget we changed it to be this way? |
| Attachment 1: 220628_1117_Rollover0xE.png
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| Attachment 2: 220628_1119_Merger_Stats_0x7.png
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| Attachment 3: NewMerger_Dump.txt
|
MERGE Data Link (17671): block sequence error: ID 2, expected 462; received 0
MERGE Data Link (17669): block sequence error: ID 0, expected 461; received 0
MERGE Data Link (17672): block sequence error: ID 3, expected 462; received 0
MERGE Data Link (17670): block sequence error: ID 1, expected 462; received 0
MERGE Data Link (17674): block sequence error: ID 5, expected 463; received 0
MERGE Data Link (17676): block sequence error: ID 7, expected 462; received 0
MERGE Data Link (17675): block sequence error: ID 6, expected 461; received 0
MERGE Data Link (17673): block sequence error: ID 4, expected 462; received 0
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
MERGE Actor (17699): Working with 0 from 8 data sources
|
|
507
|
Tue Jun 28 09:37:19 2022 |
NH | Tues 28 June 08:00- |
Experiment over
10:37 - Stop DAQ & Tape
S4 enters controlled access and they uncable bPlas
Will dismount AIDA snout after |
|
506
|
Mon Jun 27 23:11:47 2022 |
TD | Tuesday 28 June 00:00-08:00 |
00:07 Zero stats & all histograms
ASIC settings 2021Apr29-13-16-00
slow comparator 0x64 -> 0xa
all waveform AD9252 ADCs disabled
all fast discs disabled
BNC PB-5 settings (to p+n FEE64s only)
amplitude 1.0V
attenuator x1
decay time 1ms
polarity +
frequency 22Hz
analysis of file S505/R5_896 - attachment 1
zero timewarps
deadtime all FEE64s << 1%
All system wide checks OK *except* WR & FPGA errors - attachments 2 & 3
adc data item stats - attachment 4
FEE64 temps OK - attachment 5
DSSSD bias & leakage currents OK - attachment 6 & 7
00:15 Check ASIC control all FEE64s, all ASICs
02:03
analysis of file S505/R5_914 - attachment 8
zero timewarps
deadtime all FEE64s << 1%
per FEE64 1.8.H spectra - attachments 9 & 10
per p+n FEE64 1.8.L spectra - attachment 11
aida01 pulser peak width 94 ch FWHM
per FEE64 stat & rate spectra - attachments 12 & 13
All system wide checks OK *except* WR & FPGA errors - attachments 14 & 15
adc data item stats - attachment 16
FEE64 temps OK - attachment 17
DSSSD bias & leakage currents OK - attachment 18
03:31 S505 PI Anabel declares experiment end - following periods of beam loss and FRS DAQ issues today
03:41
analysis of file S505/R5_926 - attachment 19
zero timewarps
deadtime all FEE64s << 1%
All system wide checks OK *except* WR & FPGA errors - attachments 20 & 21
adc data item stats - attachment 22
FEE64 temps OK - attachment 23
DSSSD bias & leakage currents OK - attachment 24
07:00
analysis of file S505/R5_954 - attachment 25
zero timewarps
deadtime all FEE64s << 1%
All system wide checks OK *except* WR & FPGA errors - attachments 26 & 27
adc data item stats - attachment 28
FEE64 temps OK - attachment 29
DSSSD bias & leakage currents OK - attachment 30 |
| Attachment 1: R5_896
|
*** TDR format 3.3.0 analyser - TD - May 2021
*** ERROR: READ I/O error: 5002
blocks: 32000
ADC data format: 261821326 ( 595374.9 Hz)
Other data format: 98676 ( 224.4 Hz)
Sample trace data format: 0 ( 0.0 Hz)
Undefined format: 0 ( 0.0 Hz)
Other data format type: PAUSE: 406 ( 0.9 Hz)
RESUME: 406 ( 0.9 Hz)
SYNC100: 33638 ( 76.5 Hz)
WR48-63: 33638 ( 76.5 Hz)
FEE64 disc: 0 ( 0.0 Hz)
MBS info: 30588 ( 69.6 Hz)
Other info: 0 ( 0.0 Hz)
ADC data range bit set: 0 ( 0.0 Hz)
Timewarps: ADC: 0 ( 0.0 Hz)
PAUSE: 0 ( 0.0 Hz)
RESUME: 0 ( 0.0 Hz)
SYNC100: 0 ( 0.0 Hz)
WR48-63: 0 ( 0.0 Hz)
FEE64 disc: 0 ( 0.0 Hz)
MBS info: 0 ( 0.0 Hz)
Undefined: 0 ( 0.0 Hz)
Sample trace: 0 ( 0.0 Hz)
*** Timestamp elapsed time: 439.759 s
FEE elapsed dead time(s) elapsed idle time(s)
0 0.000 0.000
1 1.599 0.000
2 0.000 0.000
3 0.043 0.000
4 0.000 153.964
5 0.000 0.000
6 0.053 0.000
7 0.015 0.000
8 0.000 0.000
9 0.000 0.000
10 0.000 0.000
11 0.000 0.000
12 0.000 0.000
13 0.000 0.000
14 0.000 0.000
15 0.000 0.000
16 0.000 0.000
17 0.000 0.000
18 0.000 0.000
19 0.000 0.000
20 0.000 0.000
21 0.000 0.000
22 0.000 0.000
23 0.000 0.000
24 0.000 0.000
25 0.000 0.000
26 0.000 0.000
27 0.000 0.000
28 0.000 0.000
29 0.000 0.000
30 0.000 0.000
31 0.000 0.000
32 0.000 0.000
*** Statistics
FEE ADC Data Other Data Sample Undefined Pause Resume SYNC100 WR48-63 Disc MBS Other HEC Data
0 19090298 35782 0 0 0 0 2597 2597 0 30588 0 0
1 70343282 19202 0 0 400 400 9201 9201 0 0 0 0
2 10361360 2782 0 0 0 0 1391 1391 0 0 0 0
3 39578798 10102 0 0 3 3 5048 5048 0 0 0 0
4 3065688 742 0 0 0 0 371 371 0 0 0 0
5 15482560 3946 0 0 0 0 1973 1973 0 0 0 0
6 51969876 12870 0 0 2 2 6433 6433 0 0 0 0
7 51929464 13250 0 0 1 1 6624 6624 0 0 0 0
8 0 0 0 0 0 0 0 0 0 0 0 0
9 0 0 0 0 0 0 0 0 0 0 0 0
10 0 0 0 0 0 0 0 0 0 0 0 0
11 0 0 0 0 0 0 0 0 0 0 0 0
12 0 0 0 0 0 0 0 0 0 0 0 0
13 0 0 0 0 0 0 0 0 0 0 0 0
14 0 0 0 0 0 0 0 0 0 0 0 0
15 0 0 0 0 0 0 0 0 0 0 0 0
16 0 0 0 0 0 0 0 0 0 0 0 0
17 0 0 0 0 0 0 0 0 0 0 0 0
18 0 0 0 0 0 0 0 0 0 0 0 0
19 0 0 0 0 0 0 0 0 0 0 0 0
20 0 0 0 0 0 0 0 0 0 0 0 0
21 0 0 0 0 0 0 0 0 0 0 0 0
22 0 0 0 0 0 0 0 0 0 0 0 0
23 0 0 0 0 0 0 0 0 0 0 0 0
24 0 0 0 0 0 0 0 0 0 0 0 0
25 0 0 0 0 0 0 0 0 0 0 0 0
26 0 0 0 0 0 0 0 0 0 0 0 0
27 0 0 0 0 0 0 0 0 0 0 0 0
28 0 0 0 0 0 0 0 0 0 0 0 0
29 0 0 0 0 0 0 0 0 0 0 0 0
30 0 0 0 0 0 0 0 0 0 0 0 0
31 0 0 0 0 0 0 0 0 0 0 0 0
32 0 0 0 0 0 0 0 0 0 0 0 0
*** Timewarps
FEE ADC Pause Resume SYNC100 WR48-63 Disc MBS Undefined Samples
0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0
2 0 0 0 0 0 0 0 0 0
3 0 0 0 0 0 0 0 0 0
4 0 0 0 0 0 0 0 0 0
5 0 0 0 0 0 0 0 0 0
6 0 0 0 0 0 0 0 0 0
7 0 0 0 0 0 0 0 0 0
8 0 0 0 0 0 0 0 0 0
9 0 0 0 0 0 0 0 0 0
10 0 0 0 0 0 0 0 0 0
11 0 0 0 0 0 0 0 0 0
12 0 0 0 0 0 0 0 0 0
13 0 0 0 0 0 0 0 0 0
14 0 0 0 0 0 0 0 0 0
15 0 0 0 0 0 0 0 0 0
16 0 0 0 0 0 0 0 0 0
17 0 0 0 0 0 0 0 0 0
18 0 0 0 0 0 0 0 0 0
19 0 0 0 0 0 0 0 0 0
20 0 0 0 0 0 0 0 0 0
21 0 0 0 0 0 0 0 0 0
22 0 0 0 0 0 0 0 0 0
23 0 0 0 0 0 0 0 0 0
24 0 0 0 0 0 0 0 0 0
25 0 0 0 0 0 0 0 0 0
26 0 0 0 0 0 0 0 0 0
27 0 0 0 0 0 0 0 0 0
28 0 0 0 0 0 0 0 0 0
29 0 0 0 0 0 0 0 0 0
30 0 0 0 0 0 0 0 0 0
31 0 0 0 0 0 0 0 0 0
32 0 0 0 0 0 0 0 0 0
*** Program elapsed time: 35.371s ( 904.697 blocks/s, 56.544 Mb/s)
|
| Attachment 2: Screenshot_from_2022-06-28_00-06-58.png
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| Attachment 3: Screenshot_from_2022-06-28_00-06-35.png
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| Attachment 4: Screenshot_from_2022-06-28_00-06-00.png
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| Attachment 5: Screenshot_from_2022-06-28_00-05-30.png
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| Attachment 6: Screenshot_from_2022-06-28_00-04-42.png
|
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| Attachment 7: Screenshot_from_2022-06-28_00-03-56.png
|
|
| Attachment 8: R5_914
|
*** TDR format 3.3.0 analyser - TD - May 2021
*** ERROR: READ I/O error: 5002
blocks: 32000
ADC data format: 261460369 ( 646962.6 Hz)
Other data format: 459631 ( 1137.3 Hz)
Sample trace data format: 0 ( 0.0 Hz)
Undefined format: 0 ( 0.0 Hz)
Other data format type: PAUSE: 616 ( 1.5 Hz)
RESUME: 616 ( 1.5 Hz)
SYNC100: 33505 ( 82.9 Hz)
WR48-63: 33505 ( 82.9 Hz)
FEE64 disc: 0 ( 0.0 Hz)
MBS info: 391389 ( 968.5 Hz)
Other info: 0 ( 0.0 Hz)
ADC data range bit set: 131720 ( 325.9 Hz)
Timewarps: ADC: 0 ( 0.0 Hz)
PAUSE: 0 ( 0.0 Hz)
RESUME: 0 ( 0.0 Hz)
SYNC100: 0 ( 0.0 Hz)
WR48-63: 0 ( 0.0 Hz)
FEE64 disc: 0 ( 0.0 Hz)
MBS info: 0 ( 0.0 Hz)
Undefined: 0 ( 0.0 Hz)
Sample trace: 0 ( 0.0 Hz)
*** Timestamp elapsed time: 404.135 s
FEE elapsed dead time(s) elapsed idle time(s)
0 0.615 0.000
1 2.119 0.000
2 0.420 0.000
3 0.323 0.000
4 0.124 111.840
5 0.000 0.000
6 0.696 0.000
7 0.001 0.000
8 0.000 0.000
9 0.000 0.000
10 0.000 0.000
11 0.000 0.000
12 0.000 0.000
13 0.000 0.000
14 0.000 0.000
15 0.000 0.000
16 0.000 0.000
17 0.000 0.000
18 0.000 0.000
19 0.000 0.000
20 0.000 0.000
21 0.000 0.000
22 0.000 0.000
23 0.000 0.000
24 0.000 0.000
25 0.000 0.000
26 0.000 0.000
27 0.000 0.000
28 0.000 0.000
29 0.000 0.000
30 0.000 0.000
31 0.000 0.000
32 0.000 0.000
*** Statistics
FEE ADC Data Other Data Sample Undefined Pause Resume SYNC100 WR48-63 Disc MBS Other HEC Data
0 19284409 33077 0 0 6 6 2512 2512 0 28041 0 31815
1 69379431 18886 0 0 391 391 9052 9052 0 0 0 26209
2 20984122 96945 0 0 6 6 2775 2775 0 91383 0 19775
3 56761004 105837 0 0 202 202 7127 7127 0 91179 0 9889
4 3261224 838 0 0 2 2 417 417 0 0 0 9818
5 13707273 3434 0 0 0 0 1717 1717 0 0 0 11918
6 42321326 100064 0 0 8 8 5351 5351 0 89346 0 17237
7 35761580 100550 0 0 1 1 4554 4554 0 91440 0 5059
8 0 0 0 0 0 0 0 0 0 0 0 0
9 0 0 0 0 0 0 0 0 0 0 0 0
10 0 0 0 0 0 0 0 0 0 0 0 0
11 0 0 0 0 0 0 0 0 0 0 0 0
12 0 0 0 0 0 0 0 0 0 0 0 0
13 0 0 0 0 0 0 0 0 0 0 0 0
14 0 0 0 0 0 0 0 0 0 0 0 0
15 0 0 0 0 0 0 0 0 0 0 0 0
16 0 0 0 0 0 0 0 0 0 0 0 0
17 0 0 0 0 0 0 0 0 0 0 0 0
18 0 0 0 0 0 0 0 0 0 0 0 0
19 0 0 0 0 0 0 0 0 0 0 0 0
20 0 0 0 0 0 0 0 0 0 0 0 0
21 0 0 0 0 0 0 0 0 0 0 0 0
22 0 0 0 0 0 0 0 0 0 0 0 0
23 0 0 0 0 0 0 0 0 0 0 0 0
24 0 0 0 0 0 0 0 0 0 0 0 0
25 0 0 0 0 0 0 0 0 0 0 0 0
26 0 0 0 0 0 0 0 0 0 0 0 0
27 0 0 0 0 0 0 0 0 0 0 0 0
28 0 0 0 0 0 0 0 0 0 0 0 0
29 0 0 0 0 0 0 0 0 0 0 0 0
30 0 0 0 0 0 0 0 0 0 0 0 0
31 0 0 0 0 0 0 0 0 0 0 0 0
32 0 0 0 0 0 0 0 0 0 0 0 0
*** Timewarps
FEE ADC Pause Resume SYNC100 WR48-63 Disc MBS Undefined Samples
0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0
2 0 0 0 0 0 0 0 0 0
3 0 0 0 0 0 0 0 0 0
4 0 0 0 0 0 0 0 0 0
5 0 0 0 0 0 0 0 0 0
6 0 0 0 0 0 0 0 0 0
7 0 0 0 0 0 0 0 0 0
8 0 0 0 0 0 0 0 0 0
9 0 0 0 0 0 0 0 0 0
10 0 0 0 0 0 0 0 0 0
11 0 0 0 0 0 0 0 0 0
12 0 0 0 0 0 0 0 0 0
13 0 0 0 0 0 0 0 0 0
14 0 0 0 0 0 0 0 0 0
15 0 0 0 0 0 0 0 0 0
16 0 0 0 0 0 0 0 0 0
17 0 0 0 0 0 0 0 0 0
18 0 0 0 0 0 0 0 0 0
19 0 0 0 0 0 0 0 0 0
20 0 0 0 0 0 0 0 0 0
21 0 0 0 0 0 0 0 0 0
22 0 0 0 0 0 0 0 0 0
23 0 0 0 0 0 0 0 0 0
24 0 0 0 0 0 0 0 0 0
25 0 0 0 0 0 0 0 0 0
26 0 0 0 0 0 0 0 0 0
27 0 0 0 0 0 0 0 0 0
28 0 0 0 0 0 0 0 0 0
29 0 0 0 0 0 0 0 0 0
30 0 0 0 0 0 0 0 0 0
31 0 0 0 0 0 0 0 0 0
32 0 0 0 0 0 0 0 0 0
*** Program elapsed time: 35.648s ( 897.667 blocks/s, 56.104 Mb/s)
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| Attachment 9: Screenshot_from_2022-06-28_02-14-50.png
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| Attachment 10: Screenshot_from_2022-06-28_02-13-46.png
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| Attachment 11: Screenshot_from_2022-06-28_02-12-22.png
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| Attachment 12: Screenshot_from_2022-06-28_02-11-10.png
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| Attachment 13: Screenshot_from_2022-06-28_02-10-07.png
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| Attachment 14: Screenshot_from_2022-06-28_02-08-49.png
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| Attachment 15: Screenshot_from_2022-06-28_02-05-26.png
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| Attachment 16: Screenshot_from_2022-06-28_02-04-36.png
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| Attachment 17: Screenshot_from_2022-06-28_02-04-11.png
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| Attachment 18: Screenshot_from_2022-06-28_02-03-39.png
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| Attachment 19: R5_926
|
*** TDR format 3.3.0 analyser - TD - May 2021
*** ERROR: READ I/O error: 5002
blocks: 32000
ADC data format: 261820610 ( 589706.0 Hz)
Other data format: 99390 ( 223.9 Hz)
Sample trace data format: 0 ( 0.0 Hz)
Undefined format: 0 ( 0.0 Hz)
Other data format type: PAUSE: 624 ( 1.4 Hz)
RESUME: 624 ( 1.4 Hz)
SYNC100: 33654 ( 75.8 Hz)
WR48-63: 33654 ( 75.8 Hz)
FEE64 disc: 0 ( 0.0 Hz)
MBS info: 30834 ( 69.4 Hz)
Other info: 0 ( 0.0 Hz)
ADC data range bit set: 0 ( 0.0 Hz)
Timewarps: ADC: 0 ( 0.0 Hz)
PAUSE: 0 ( 0.0 Hz)
RESUME: 0 ( 0.0 Hz)
SYNC100: 0 ( 0.0 Hz)
WR48-63: 0 ( 0.0 Hz)
FEE64 disc: 0 ( 0.0 Hz)
MBS info: 0 ( 0.0 Hz)
Undefined: 0 ( 0.0 Hz)
Sample trace: 0 ( 0.0 Hz)
*** Timestamp elapsed time: 443.985 s
FEE elapsed dead time(s) elapsed idle time(s)
0 0.000 0.000
1 1.081 0.000
2 0.000 0.000
3 0.281 0.000
4 0.000 152.429
5 0.000 0.000
6 0.000 0.000
7 0.000 0.000
8 0.000 0.000
9 0.000 0.000
10 0.000 0.000
11 0.000 0.000
12 0.000 0.000
13 0.000 0.000
14 0.000 0.000
15 0.000 0.000
16 0.000 0.000
17 0.000 0.000
18 0.000 0.000
19 0.000 0.000
20 0.000 0.000
21 0.000 0.000
22 0.000 0.000
23 0.000 0.000
24 0.000 0.000
25 0.000 0.000
26 0.000 0.000
27 0.000 0.000
28 0.000 0.000
29 0.000 0.000
30 0.000 0.000
31 0.000 0.000
32 0.000 0.000
*** Statistics
FEE ADC Data Other Data Sample Undefined Pause Resume SYNC100 WR48-63 Disc MBS Other HEC Data
0 15622398 34978 0 0 0 0 2072 2072 0 30834 0 0
1 68236330 18574 0 0 381 381 8906 8906 0 0 0 0
2 18744892 4984 0 0 0 0 2492 2492 0 0 0 0
3 59875268 15514 0 0 243 243 7514 7514 0 0 0 0
4 2759883 664 0 0 0 0 332 332 0 0 0 0
5 13541412 3478 0 0 0 0 1739 1739 0 0 0 0
6 45470554 11726 0 0 0 0 5863 5863 0 0 0 0
7 37569873 9472 0 0 0 0 4736 4736 0 0 0 0
8 0 0 0 0 0 0 0 0 0 0 0 0
9 0 0 0 0 0 0 0 0 0 0 0 0
10 0 0 0 0 0 0 0 0 0 0 0 0
11 0 0 0 0 0 0 0 0 0 0 0 0
12 0 0 0 0 0 0 0 0 0 0 0 0
13 0 0 0 0 0 0 0 0 0 0 0 0
14 0 0 0 0 0 0 0 0 0 0 0 0
15 0 0 0 0 0 0 0 0 0 0 0 0
16 0 0 0 0 0 0 0 0 0 0 0 0
17 0 0 0 0 0 0 0 0 0 0 0 0
18 0 0 0 0 0 0 0 0 0 0 0 0
19 0 0 0 0 0 0 0 0 0 0 0 0
20 0 0 0 0 0 0 0 0 0 0 0 0
21 0 0 0 0 0 0 0 0 0 0 0 0
22 0 0 0 0 0 0 0 0 0 0 0 0
23 0 0 0 0 0 0 0 0 0 0 0 0
24 0 0 0 0 0 0 0 0 0 0 0 0
25 0 0 0 0 0 0 0 0 0 0 0 0
26 0 0 0 0 0 0 0 0 0 0 0 0
27 0 0 0 0 0 0 0 0 0 0 0 0
28 0 0 0 0 0 0 0 0 0 0 0 0
29 0 0 0 0 0 0 0 0 0 0 0 0
30 0 0 0 0 0 0 0 0 0 0 0 0
31 0 0 0 0 0 0 0 0 0 0 0 0
32 0 0 0 0 0 0 0 0 0 0 0 0
*** Timewarps
FEE ADC Pause Resume SYNC100 WR48-63 Disc MBS Undefined Samples
0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0
2 0 0 0 0 0 0 0 0 0
3 0 0 0 0 0 0 0 0 0
4 0 0 0 0 0 0 0 0 0
5 0 0 0 0 0 0 0 0 0
6 0 0 0 0 0 0 0 0 0
7 0 0 0 0 0 0 0 0 0
8 0 0 0 0 0 0 0 0 0
9 0 0 0 0 0 0 0 0 0
10 0 0 0 0 0 0 0 0 0
11 0 0 0 0 0 0 0 0 0
12 0 0 0 0 0 0 0 0 0
13 0 0 0 0 0 0 0 0 0
14 0 0 0 0 0 0 0 0 0
15 0 0 0 0 0 0 0 0 0
16 0 0 0 0 0 0 0 0 0
17 0 0 0 0 0 0 0 0 0
18 0 0 0 0 0 0 0 0 0
19 0 0 0 0 0 0 0 0 0
20 0 0 0 0 0 0 0 0 0
21 0 0 0 0 0 0 0 0 0
22 0 0 0 0 0 0 0 0 0
23 0 0 0 0 0 0 0 0 0
24 0 0 0 0 0 0 0 0 0
25 0 0 0 0 0 0 0 0 0
26 0 0 0 0 0 0 0 0 0
27 0 0 0 0 0 0 0 0 0
28 0 0 0 0 0 0 0 0 0
29 0 0 0 0 0 0 0 0 0
30 0 0 0 0 0 0 0 0 0
31 0 0 0 0 0 0 0 0 0
32 0 0 0 0 0 0 0 0 0
*** Program elapsed time: 35.045s ( 913.114 blocks/s, 57.070 Mb/s)
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| Attachment 20: Screenshot_from_2022-06-28_03-44-20.png
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| Attachment 21: Screenshot_from_2022-06-28_03-44-00.png
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| Attachment 22: Screenshot_from_2022-06-28_03-43-05.png
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| Attachment 23: Screenshot_from_2022-06-28_03-41-50.png
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| Attachment 24: Screenshot_from_2022-06-28_03-41-21.png
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| Attachment 25: R5_954
|
*** TDR format 3.3.0 analyser - TD - May 2021
*** ERROR: READ I/O error: 5002
blocks: 32000
ADC data format: 261819650 ( 564425.6 Hz)
Other data format: 100350 ( 216.3 Hz)
Sample trace data format: 0 ( 0.0 Hz)
Undefined format: 0 ( 0.0 Hz)
Other data format type: PAUSE: 346 ( 0.7 Hz)
RESUME: 346 ( 0.7 Hz)
SYNC100: 33728 ( 72.7 Hz)
WR48-63: 33728 ( 72.7 Hz)
FEE64 disc: 0 ( 0.0 Hz)
MBS info: 32202 ( 69.4 Hz)
Other info: 0 ( 0.0 Hz)
ADC data range bit set: 0 ( 0.0 Hz)
Timewarps: ADC: 0 ( 0.0 Hz)
PAUSE: 0 ( 0.0 Hz)
RESUME: 0 ( 0.0 Hz)
SYNC100: 0 ( 0.0 Hz)
WR48-63: 0 ( 0.0 Hz)
FEE64 disc: 0 ( 0.0 Hz)
MBS info: 0 ( 0.0 Hz)
Undefined: 0 ( 0.0 Hz)
Sample trace: 0 ( 0.0 Hz)
*** Timestamp elapsed time: 463.869 s
FEE elapsed dead time(s) elapsed idle time(s)
0 0.000 0.000
1 0.860 0.000
2 0.000 16.297
3 0.000 0.000
4 0.000 130.996
5 0.000 0.000
6 0.000 0.000
7 0.000 0.000
8 0.000 0.000
9 0.000 0.000
10 0.000 0.000
11 0.000 0.000
12 0.000 0.000
13 0.000 0.000
14 0.000 0.000
15 0.000 0.000
16 0.000 0.000
17 0.000 0.000
18 0.000 0.000
19 0.000 0.000
20 0.000 0.000
21 0.000 0.000
22 0.000 0.000
23 0.000 0.000
24 0.000 0.000
25 0.000 0.000
26 0.000 0.000
27 0.000 0.000
28 0.000 0.000
29 0.000 0.000
30 0.000 0.000
31 0.000 0.000
32 0.000 0.000
*** Statistics
FEE ADC Data Other Data Sample Undefined Pause Resume SYNC100 WR48-63 Disc MBS Other HEC Data
0 19510795 37524 0 0 0 0 2661 2661 0 32202 0 0
1 71776267 19370 0 0 343 343 9342 9342 0 0 0 0
2 7596519 1752 0 0 0 0 876 876 0 0 0 0
3 39174917 10150 0 0 0 0 5075 5075 0 0 0 0
4 3312486 838 0 0 0 0 419 419 0 0 0 0
5 15419570 4004 0 0 0 0 2002 2002 0 0 0 0
6 56857618 14472 0 0 3 3 7233 7233 0 0 0 0
7 48171478 12240 0 0 0 0 6120 6120 0 0 0 0
8 0 0 0 0 0 0 0 0 0 0 0 0
9 0 0 0 0 0 0 0 0 0 0 0 0
10 0 0 0 0 0 0 0 0 0 0 0 0
11 0 0 0 0 0 0 0 0 0 0 0 0
12 0 0 0 0 0 0 0 0 0 0 0 0
13 0 0 0 0 0 0 0 0 0 0 0 0
14 0 0 0 0 0 0 0 0 0 0 0 0
15 0 0 0 0 0 0 0 0 0 0 0 0
16 0 0 0 0 0 0 0 0 0 0 0 0
17 0 0 0 0 0 0 0 0 0 0 0 0
18 0 0 0 0 0 0 0 0 0 0 0 0
19 0 0 0 0 0 0 0 0 0 0 0 0
20 0 0 0 0 0 0 0 0 0 0 0 0
21 0 0 0 0 0 0 0 0 0 0 0 0
22 0 0 0 0 0 0 0 0 0 0 0 0
23 0 0 0 0 0 0 0 0 0 0 0 0
24 0 0 0 0 0 0 0 0 0 0 0 0
25 0 0 0 0 0 0 0 0 0 0 0 0
26 0 0 0 0 0 0 0 0 0 0 0 0
27 0 0 0 0 0 0 0 0 0 0 0 0
28 0 0 0 0 0 0 0 0 0 0 0 0
29 0 0 0 0 0 0 0 0 0 0 0 0
30 0 0 0 0 0 0 0 0 0 0 0 0
31 0 0 0 0 0 0 0 0 0 0 0 0
32 0 0 0 0 0 0 0 0 0 0 0 0
*** Timewarps
FEE ADC Pause Resume SYNC100 WR48-63 Disc MBS Undefined Samples
0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0
2 0 0 0 0 0 0 0 0 0
3 0 0 0 0 0 0 0 0 0
4 0 0 0 0 0 0 0 0 0
5 0 0 0 0 0 0 0 0 0
6 0 0 0 0 0 0 0 0 0
7 0 0 0 0 0 0 0 0 0
8 0 0 0 0 0 0 0 0 0
9 0 0 0 0 0 0 0 0 0
10 0 0 0 0 0 0 0 0 0
11 0 0 0 0 0 0 0 0 0
12 0 0 0 0 0 0 0 0 0
13 0 0 0 0 0 0 0 0 0
14 0 0 0 0 0 0 0 0 0
15 0 0 0 0 0 0 0 0 0
16 0 0 0 0 0 0 0 0 0
17 0 0 0 0 0 0 0 0 0
18 0 0 0 0 0 0 0 0 0
19 0 0 0 0 0 0 0 0 0
20 0 0 0 0 0 0 0 0 0
21 0 0 0 0 0 0 0 0 0
22 0 0 0 0 0 0 0 0 0
23 0 0 0 0 0 0 0 0 0
24 0 0 0 0 0 0 0 0 0
25 0 0 0 0 0 0 0 0 0
26 0 0 0 0 0 0 0 0 0
27 0 0 0 0 0 0 0 0 0
28 0 0 0 0 0 0 0 0 0
29 0 0 0 0 0 0 0 0 0
30 0 0 0 0 0 0 0 0 0
31 0 0 0 0 0 0 0 0 0
32 0 0 0 0 0 0 0 0 0
*** Program elapsed time: 35.318s ( 906.044 blocks/s, 56.628 Mb/s)
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| Attachment 26: Screenshot_from_2022-06-28_07-03-01.png
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| Attachment 27: Screenshot_from_2022-06-28_07-02-34.png
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| Attachment 28: Screenshot_from_2022-06-28_07-01-31.png
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| Attachment 29: Screenshot_from_2022-06-28_07-01-03.png
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| Attachment 30: Screenshot_from_2022-06-28_07-00-31.png
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|
505
|
Mon Jun 27 17:03:09 2022 |
MA | Monday 27th June 16:00-00:00 |
16:00 Took over the shift from OH no beam yet.
18:00 Still no beam yet.
Statistics, Temperature, Current are checked and attached 1-3
system wide checks same as last updated in the previoues shift.
22:00 The beam is back but not taking data yet! FRS team doing some checkings
Statistics, Temperature, Current are checked and attached 4-6
system wide checks same as last updated in the previoues shift.
23:30 beam is back and taking data |
| Attachment 1: Statistics2022-06-27_18-02-25.png
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|
| Attachment 2: Temperature2022-06-27_18-01-14.png
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|
| Attachment 3: Current2022-06-27_17-59-55.png
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| Attachment 4: Statics2022-06-27_22-12-07.png
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| Attachment 5: Temperature2022-06-27_22-11-21.png
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|
| Attachment 6: Current2022-06-27_22-10-12.png
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|
|
504
|
Mon Jun 27 06:45:22 2022 |
OH | Monday 27th June 08:00-16:00 |
07:45 Spoke to David and the beam has been gone since about 05:30
Reason for the loss of beam is a vacuum issue before the FRS
They are waiting for the experts
08:31 Statistics ok - attachment 1
Temperature ok - attachment 2
Bias and leakage currrents ok - attachment 3
ASIC clock check ok
Base Current Difference
aida07 fault 0xc53d : 0xc5cf : 146
aida08 fault 0xf1be : 0xf2ba : 252
White Rabbit error counter test result: Passed 6, Failed 2
Base Current Difference
aida07 fault 0x2a : 0x41 : 23
Currently on file R5_771
Analysis of file R5_770 (No beam) - attachment 4
Around 0.25% deadtime on AIDA02 rest even less
09:02 Current free HDD space 965 GB
Current tape server rate 4979 kB/s
Free space taking data rate at 5700 kB/s (Closer to beam value) 47 hours
11:41 Statistics ok - attachment 5
Temperatures ok - attachment 6
Bias and leakage currents ok - attachment 7
ASIC clock check ok
Base Current Difference
aida07 fault 0xc53d : 0xc5cf : 146
aida08 fault 0xf1be : 0xf2ba : 252
White Rabbit error counter test result: Passed 6, Failed 2
Base Current Difference
aida07 fault 0x2a : 0x41 : 23
FPGA Timestamp error counter test result: Passed 7, Failed 1
Note that there has been no change in the White Rabbit errors or FPGA faults since very early morning.
Could the rate of accrual in errors be proportional to the data rate. Faster data rate, errors occur more frequently? |
| Attachment 1: 220626_0830_Stats.png
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|
| Attachment 2: 220626_0830_Temp.png
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| Attachment 3: 220626_0831_Bias.png
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| Attachment 4: R5_770_analysis.txt
|
*** TDR format 3.3.0 analyser - TD - May 2021
*** ERROR: READ I/O error: 5002
blocks: 32000
ADC data format: 261823568 ( 639881.5 Hz)
Other data format: 96432 ( 235.7 Hz)
Sample trace data format: 0 ( 0.0 Hz)
Undefined format: 0 ( 0.0 Hz)
Other data format type: PAUSE: 451 ( 1.1 Hz)
RESUME: 451 ( 1.1 Hz)
SYNC100: 33524 ( 81.9 Hz)
WR48-63: 33524 ( 81.9 Hz)
FEE64 disc: 0 ( 0.0 Hz)
MBS info: 28482 ( 69.6 Hz)
Other info: 0 ( 0.0 Hz)
ADC data range bit set: 0 ( 0.0 Hz)
Timewarps: ADC: 0 ( 0.0 Hz)
PAUSE: 0 ( 0.0 Hz)
RESUME: 0 ( 0.0 Hz)
SYNC100: 0 ( 0.0 Hz)
WR48-63: 0 ( 0.0 Hz)
FEE64 disc: 0 ( 0.0 Hz)
MBS info: 0 ( 0.0 Hz)
Undefined: 0 ( 0.0 Hz)
Sample trace: 0 ( 0.0 Hz)
*** Timestamp elapsed time: 409.175 s
FEE elapsed dead time(s) elapsed idle time(s)
0 0.033 0.000
1 1.307 0.000
2 0.000 0.000
3 0.206 0.000
4 0.000 157.882
5 0.000 0.000
6 0.000 0.000
7 0.139 0.000
8 0.000 0.000
9 0.000 0.000
10 0.000 0.000
11 0.000 0.000
12 0.000 0.000
13 0.000 0.000
14 0.000 0.000
15 0.000 0.000
16 0.000 0.000
17 0.000 0.000
18 0.000 0.000
19 0.000 0.000
20 0.000 0.000
21 0.000 0.000
22 0.000 0.000
23 0.000 0.000
24 0.000 0.000
25 0.000 0.000
26 0.000 0.000
27 0.000 0.000
28 0.000 0.000
29 0.000 0.000
30 0.000 0.000
31 0.000 0.000
32 0.000 0.000
*** Statistics
FEE ADC Data Other Data Sample Undefined Pause Resume SYNC100 WR48-63 Disc MBS Other HEC Data
0 20319054 33950 0 0 1 1 2733 2733 0 28482 0 0
1 68104715 18442 0 0 318 318 8903 8903 0 0 0 0
2 24150534 6320 0 0 0 0 3160 3160 0 0 0 0
3 55928626 14410 0 0 131 131 7074 7074 0 0 0 0
4 2503858 618 0 0 0 0 309 309 0 0 0 0
5 12980974 3340 0 0 0 0 1670 1670 0 0 0 0
6 41271038 10344 0 0 0 0 5172 5172 0 0 0 0
7 36564769 9008 0 0 1 1 4503 4503 0 0 0 0
8 0 0 0 0 0 0 0 0 0 0 0 0
9 0 0 0 0 0 0 0 0 0 0 0 0
10 0 0 0 0 0 0 0 0 0 0 0 0
11 0 0 0 0 0 0 0 0 0 0 0 0
12 0 0 0 0 0 0 0 0 0 0 0 0
13 0 0 0 0 0 0 0 0 0 0 0 0
14 0 0 0 0 0 0 0 0 0 0 0 0
15 0 0 0 0 0 0 0 0 0 0 0 0
16 0 0 0 0 0 0 0 0 0 0 0 0
17 0 0 0 0 0 0 0 0 0 0 0 0
18 0 0 0 0 0 0 0 0 0 0 0 0
19 0 0 0 0 0 0 0 0 0 0 0 0
20 0 0 0 0 0 0 0 0 0 0 0 0
21 0 0 0 0 0 0 0 0 0 0 0 0
22 0 0 0 0 0 0 0 0 0 0 0 0
23 0 0 0 0 0 0 0 0 0 0 0 0
24 0 0 0 0 0 0 0 0 0 0 0 0
25 0 0 0 0 0 0 0 0 0 0 0 0
26 0 0 0 0 0 0 0 0 0 0 0 0
27 0 0 0 0 0 0 0 0 0 0 0 0
28 0 0 0 0 0 0 0 0 0 0 0 0
29 0 0 0 0 0 0 0 0 0 0 0 0
30 0 0 0 0 0 0 0 0 0 0 0 0
31 0 0 0 0 0 0 0 0 0 0 0 0
32 0 0 0 0 0 0 0 0 0 0 0 0
*** Timewarps
FEE ADC Pause Resume SYNC100 WR48-63 Disc MBS Undefined Samples
0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0
2 0 0 0 0 0 0 0 0 0
3 0 0 0 0 0 0 0 0 0
4 0 0 0 0 0 0 0 0 0
5 0 0 0 0 0 0 0 0 0
6 0 0 0 0 0 0 0 0 0
7 0 0 0 0 0 0 0 0 0
8 0 0 0 0 0 0 0 0 0
9 0 0 0 0 0 0 0 0 0
10 0 0 0 0 0 0 0 0 0
11 0 0 0 0 0 0 0 0 0
12 0 0 0 0 0 0 0 0 0
13 0 0 0 0 0 0 0 0 0
14 0 0 0 0 0 0 0 0 0
15 0 0 0 0 0 0 0 0 0
16 0 0 0 0 0 0 0 0 0
17 0 0 0 0 0 0 0 0 0
18 0 0 0 0 0 0 0 0 0
19 0 0 0 0 0 0 0 0 0
20 0 0 0 0 0 0 0 0 0
21 0 0 0 0 0 0 0 0 0
22 0 0 0 0 0 0 0 0 0
23 0 0 0 0 0 0 0 0 0
24 0 0 0 0 0 0 0 0 0
25 0 0 0 0 0 0 0 0 0
26 0 0 0 0 0 0 0 0 0
27 0 0 0 0 0 0 0 0 0
28 0 0 0 0 0 0 0 0 0
29 0 0 0 0 0 0 0 0 0
30 0 0 0 0 0 0 0 0 0
31 0 0 0 0 0 0 0 0 0
32 0 0 0 0 0 0 0 0 0
*** Program elapsed time: 41.158s ( 777.488 blocks/s, 48.593 Mb/s)
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|
503
|
Sun Jun 26 23:04:30 2022 |
Marc | new shift - Monday 27 June 0:00 to 8:00 |
0:00 Experiment continues to run smoothly. AIDA DAQ has been rather stable. Leakage current has gone up for the past two days in both DSSDs (combination of high-Z and high-intensity beam and external high temperature).
Stats & Temperatures (VIRTEX,PSU, ASICs) all ok.
At 0:30
Stats ok - Attachment 1
Temp ok - Attachement 2
HV-LC -Attachment 3
At 2:20
Stats ok - Attachment 4
Temp ok - Attachement 5
HV-LC -Attachment 6
Wide Checks:
Clock status test result: Passed 8, Failed 0
Understand status as follows
Status bit 3 : firmware PLL that creates clocks from external clock not locked
Status bit 2 : always logic '1'
Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock
Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock
If all these bits are not set then the operation of the firmware is unreliable
ADC Calibration (same as before):
FEE64 module aida01 failed
FEE64 module aida02 failed
FEE64 module aida03 failed
FEE64 module aida04 failed
FEE64 module aida05 failed
FEE64 module aida06 failed
FEE64 module aida07 failed
FEE64 module aida08 failed
Calibration test result: Passed 0, Failed 8
If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module
WR decoder status:
Base Current Difference
aida07 fault 0xc53d : 0xc5c9 : 140
aida08 fault 0xf1be : 0xf2b2 : 244
White Rabbit error counter test result: Passed 6, Failed 2
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
FPGA timestamp check:
Base Current Difference
aida07 fault 0x2a : 0x41 : 23
FPGA Timestamp error counter test result: Passed 7, Failed 1
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
At 4:15:
Stats ok - Attachment 7
Temp ok - Attachement 8
HV-LC -Attachment 9
Wide Checks: No change
At 7:15: (no beam since ~6am -> background run)
Stats ok - Attachment 10
Temp ok - Attachement 11
HV-LC -Attachment 12
Wide Checks: No change |
| Attachment 1: Stats-Screenshot_from_2022-06-27_00-30-58.png
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| Attachment 2: Temp-Screenshot_from_2022-06-27_00-31-44.png
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| Attachment 3: HV-LC-Screenshot_from_2022-06-27_00-30-18.png
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| Attachment 4: Stats-Screenshot_from_2022-06-27_02-22-34.png
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| Attachment 5: Temp-Screenshot_from_2022-06-27_02-19-42.png
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| Attachment 6: HV-LC-Screenshot_from_2022-06-27_02-19-05.png
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| Attachment 7: Stats-Screenshot_from_2022-06-27_04-17-22.png
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| Attachment 8: Temp-Screenshot_from_2022-06-27_04-16-40.png
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| Attachment 9: HV-LC-Screenshot_from_2022-06-27_04-14-57.png
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| Attachment 10: Stats-Screenshot_from_2022-06-27_07-15-17.png
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| Attachment 11: Temp-Screenshot_from_2022-06-27_07-14-02.png
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| Attachment 12: HV-LC-Screenshot_from_2022-06-27_07-13-09.png
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|