 Wed Apr 24 15:37:59 2024, PP, 16:00-00:00 shift Wednesday 24 April 8x
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All seems OK.
Screenshots attached. |
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Wed Apr 24 18:44:05 2024, PP, 19:30 checks 8x
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All seems smooth.
Screenshots attached. |
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Tue Jun 11 18:45:37 2024, PP, Mid-shift checks, 19:45 8x
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All looks good.
Sceenshots attached. |
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Wed Jun 12 11:06:55 2024, PP, Mid-shift checks, 12:00 8x
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All seems normal.
Screenshots attached. |
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Wed Jan 18 13:40:33 2023, PJCS TD, MACB settings with either Emulator or VITAR
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When using the VETAR connected to the HDMI port of the root MACB the settings for all the MACB in the system 0x3.
This setting takes the Clock and Data line from the input HDMI and outputs it via teh HDMI output ports.
When using the Emulator connected via the SMA connectors on the back of the root MACB then the setting for the root MACB |
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Wed Mar 18 18:02:37 2020, PJCS, New Firmware loaded in all FEE64s
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Loaded new frimware into all 12 FEE64s in the system. IWR_Dec19_4.bin
Booted ok after power-cycle.
RESET/SETUP/GO all fine. |
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Wed Mar 31 12:46:10 2021, PJCS, HowTo : Calibrate the LMK3200 clock devices
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Here is a document showing how and where to calibrate the LMK3200 devices that lock to the system clock and generate the clocks for the ADCs and the
FPGA internal logic. |
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Wed Mar 31 15:40:42 2021, PJCS, Check Options files function added
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There is a new operation available in the System Functions menu in the System Wide Checks page. ( The page needs to be reset once when the FEEs are powered
before this function will appear )
Check the Options files are all the same size |
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Wed Mar 31 15:46:09 2021, PJCS, HowTo : Synchronize the ASIC clocks.
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To Synchronize the FEE64 ASIC clocks to rise at the same timestamp time use the System function Synchronise the ASIC clocks in the System
Wide Checks browser page.
The Server will read the current timestamp value and calculate, based on the number of FEEs and the access delay, a timestamp value sometime |
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Wed Apr 14 12:14:47 2021, PJCS, Corrections and changes
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14/4/21 @12:00 UK time
Corrected the failure of FADC re-calibration All modules. The problem was a missing > in the .tml file
Edited the sys.tcl file in /MIDAS/TclHttpd/Html/RunControl to comment out where the status of the waveform enable was able to stop the creation |
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Wed Apr 14 15:14:55 2021, PJCS, Note Well
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Please note that for the forseeable future the system function in the menu on the System Wide Checks browser page labelled as
"Collect the Timestamp RAM values" and "Start the Readout Timestamp error tracing"
Are for the use of engineers only unless otherwise instructed. |
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Fri May 7 19:47:54 2021, PJCS, HowTo mitigate excessive temperature in an FEE64
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After tests in the Daresbury T9 system.
Disabling the waveform ADCs in an FEE64 which is running with the FPGA over temperature will drop the FPGA temperature by 10 degrees.
To disable the ADCs open the Local Control browser window and set the ADC Control register , @2, to 0xFF |
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Wed Feb 16 10:32:52 2022, PJCS, AIDA software changes and some suggestions
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The Pi console monitor program now outputs a full date/time to file for each line of report.
The System Wide Checks has been upgraded to include a check of the PLL lock monitor counters. A baseline is taken when the software starts, or
at the users command, then subsequent operation of the command compares the current counter value with the baseline. There are two PLLs on the pcb, LMK3200, |
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Wed Jun 22 10:09:12 2022, PJCS, INFO: FEE64 supply Voltages
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Study of the FEE64 power supply distribution has yielded the following :-
The most sensitive regulator, as regards the device voltage input, is the TPS51100 that supplies the DDR memory reference voltages. This
requires +4.75 to +5.25 volts. This is supplied from the Power input connector +5v input. |
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Wed Sep 14 19:07:07 2022, PJCS, INFO : Three Merger Statistics explained
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There are three Merger statistics that can be used to better understand how the data flow through the Merger system is proceeding.
Two are from the Link task and one is from the Merger.They are all "No data buffers avaliable" with #1, #2, #3 at the end.
#1: This is incremented when the Link task has a data item to put in the queue for the Merge process but there is no room. |
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Fri Apr 16 00:47:36 2021, OH-ML, AIDA DAQ Reset
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1:18 (CET) No rate in AIDA 07.
Oscar did a AIDA DAQ reset and a quick wide check.
(Power cycle |
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Thu Sep 6 15:11:17 2018, OH, TD, Tuesday 4 September - Thursday 6 September 19x
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Attachment 1 - FEE64 temperatures illustrating (we assume) a faulty PSU temperature sensor for aida07
Attachment 2 - FEE64 temperatures following replacement of aida07
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Thu Sep 6 15:25:19 2018, OH, TD, AIDA@DESPEC Setup Photos
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Thu Sep 6 15:42:53 2018, OH, TD, FEE64 system console logs
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Kernel panics during boot cab be observed in files ttyUSB1 and ttyUSB5
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Wed Sep 19 12:40:41 2018, OH, TD, Single DSSD Installation and Tests 21x
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On the 18th of September we installed DSSD 3208-14
Was found to have problems including exponential leakage behavior
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