 Fri Jan 30 13:02:35 2015, Alfredo Estrade, [Data] R61 (207Bi source) and R62-R65 (pulser walk-through)
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Jan 22, 2015
R61: 207Bi source spectra accumulated during one afternoon. Same settings as in R49 (alpha background run,
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Thu Jan 29 15:57:01 2015, Patrick Coleman-Smith, [How To] AIDA power supply alteration document 
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I've added the power supply change document.
Please have a look and let me know if it requires further clarification.
I have ordered some plastic "pot twiddlers". |
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Wed Jan 28 16:19:05 2015, Patrick Coleman-Smith, [How To] Loading new firmware into a FEE64
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Log into the FEE64 module using telnet.
use root
enter => /usr/sbin/flash_unlock /dev/mtd2 |
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Wed Jan 28 16:12:52 2015, Tom Davinson, AIDA Tests at STFC DL - 27-28.1.15 - TD & PCS
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MSL type BB18-1000 2998-22 bias +200V I_L +3.52uA
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Thu Jan 22 14:26:10 2015, Alfredo and Tom, [DATA] R49: alpha background radioactivity
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Jan20-21, 2015
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Thu Jan 22 13:50:33 2015, Alfredo and Tom, Further measurements with filtered PSU
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Jan 20, 2015
Test settings: DSSD biased at 100V, with 3.5 uA leakage current. Pulser at 0.5 V, split and inverted for both
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Wed Jan 14 15:29:01 2015, Patrick, Filtered switch mode PSU performance
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Trying the AIDA format power supply with the simple filters installed.
The detector is attached and HV of 200v@3.8uA
Using one channel from each FEE64 as a guide to compare performance. Using the Integrate analysis function Peak width. |
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Wed Dec 3 12:13:03 2014, Alfredo Estrade, IV curve with CAEN N1419
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Measured IV curve for BB18 DSSD with new CAEN HV supply. Settings as in previous elog entry:
Detector bias CAEN N1419 Programmable HV Power Supply
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Thu Nov 20 14:05:21 2014, Tom Davinson, AIDA Tests at STFC DL - PCS, TD 20x
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Configuration per Elog entries:
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Fri Oct 24 16:02:26 2014, Alfredo Estrade, bench tests with pulser
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Performed pulser measurements with test setup at Daresbury lab, with main purpose of remembering how to operate the system! The status is similar to
what Chris observed in Elog entry #14. Confirmed ASIC settings as in entry#4 of elog.
The pulser spectra shows FWHM of ~ 13.5 ch for all FEE64 cards with no DSSD connected to the system (i.e. Kapton cables unplugged). |
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Fri Oct 24 15:05:28 2014, Patrick and Alfredo, new VHDL: FEE_Riken_Apr14_21.bin
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New VHDL loaded in NNAIDA#11,#12,#13,#14: /MIDAS/Aida/FEE_Riken_Apr14_21.bin
The code introduces the feature of turning ON or OFF individual ASICs in a FEE64 card. This is achieved by turning off the
clock signal to a individual ASIC, which then will not produce any data.
Feature controled through "ASIC readout bugger |
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Sun Oct 5 22:42:56 2014, Chris Griffin, DL tests on 02/10/14 17x
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A late entry for the work I carried out on Thursday.
With the Emco box providing the HV, the pulser peak showed double (or triple) peaks. This was not seen with the SY1527 so I thought this would
be better for looking at peak widths. |
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Thu Oct 2 15:23:38 2014, Patrick Coleman-Smith and Chris Griffin, Trial with Filtered AIDA PSU
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Assembled three more of the filter boards and installed them in the AIDA PSU with the first, wired to use the switchmode power supply.
Powered up nnaida14 first and went fine. Just the boot sequence and measure the voltages for stability.
Powered up the remainder and all was well. |
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Wed Oct 1 18:37:42 2014, Chris Griffin, 01/10/2014 Tests @ DL 11x
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Kept largely the same settings at the entry https://elog.ph.ed.ac.uk/AIDA/4
Same ASIC settings
Emco used to provide HV |
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Wed Oct 1 15:41:07 2014, Patrick Coleman-Smith, Power supply filters #3
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Measuring the signal at the FEE64 end.
+5v , -6v , +7v, +7v
The two other 'scope channels are connected by FET probes to the FEE64. I now see there is a ground connection.... so i will remove it and re-measure |
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Wed Oct 1 15:15:32 2014, Patrick Coleman-Smith, Power supply filters 14x
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2.0.L FWHM:14.26
2.15.L ( 270pF ) FWHM : 119.04
(ooops found the 'scope channel was on 20Mhz BW filter ) |
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Wed Oct 1 13:28:03 2014, Patrick Coleman-Smith, Power supply filters
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The new pcb for the power supply filter arrived.
I assembled the components ( after finding the whoops ) and connected it to the bench power supply for nnaida2.
nnaida2 functions just about the same as before but the power supply filter results seem amazing. |
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Thu Sep 25 11:53:34 2014, Patrick Coleman-Smith, Backup a step to check ASICs
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Disconnected the adaptors with the detector.
Added the adaptors with the kapton cables only attached.
Connected the pulser outputs ( pos and neg ). |
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Thu Sep 25 11:35:18 2014, Patrick Coleman-Smith, Removing the MACB from the system
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I have been wondering if the 0v path from the FEE64s to the MACB where they are joined is a possible problem.
I have been contemplating an isolated LVDS interface for the 50Mhz clock to test the idea.
Fortunately i recalled the 50Mhz internal oscillator in each FEE64. |
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Mon Sep 22 09:34:37 2014, Patrick Coleman-Smith, Clue to difference between ASICs 1&2 and 3&4
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While investigating a VHDL conundrum I have noticed that the Mux ADC serial readout clock has a 'FAST' slew rate on ASICs 1&2 and a normal slew rate
on ASICs 3&4.
Is it possible that the higher slew rate is actually better filtered by the ASIC de-coupling etc than the slower one. |