ID |
Date |
Author |
Subject |
30
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Tue Feb 10 16:01:50 2015 |
Chris Griffin, Alfredo Estrade | High data rate - Pause/Resume |
06/02/15
A look at the data rate at which Pause/Resumes start to cause missing data.
Pulser settings:
Slow comparitor thresholds were altered using the ASIC4 page to artificially increase the data rate in the ASICs.
Default settings for all modules, apart from the changing slow comp threshold.
nnaida13+14 both functioning well. nnaida11+12 both have one noisy channel contributing to high data rate.
Echoing Alfredo's previous post, using the AIDA Good Events and AIDA Data Rate from the stats page as metrics, I found there to be no Pause/Resume items present in the data up to a Good Events rate of ~250-300 kHz and Data Rate of ~1-1.2 MHz.
Around this point the data shifts very quickly from containing no Pause/Resume items to having a rate of ~18 Hz, almost as a step function. At this point the Good Events and AIDA data rate sharply reach a maximum rate of 300 kHz and 1.2 MHz respectively. The rate of AIDA SYNC data items drops sharply at this point and decreases slowly with decreasing threshold.
Included are some plots showing this for each of the modules and some summary plots.
Further to the data rate at which the appearance of Pause/Resume items causes significant data loss, I looked at what happens when you break this threshold and then come back down, i.e. do the Pause/Resume items persist?
In short, no. Starting from a threshold of 64 and working down to 1, then taking the slow comparitor threshold back to a level at which no Pause/Resumes were present, the Good Events, AIDA SYNC and AIDA Data rates all went back to their original values within a couple of refreshes of the stats screen (and stayed as such thereafter). |
Attachment 1: GoodEvts_v_thresh.png
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Attachment 2: AIDAdata_v_thresh.png
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Attachment 3: AIDAsync_v_thresh.png
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Attachment 4: PauseResume_v_thresh.png
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Attachment 5: ResumeRate_v_AIDAdata.png
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Attachment 6: ResumeRate_v_GoodEvts.png
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14
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Wed Oct 1 18:37:42 2014 |
Chris Griffin | 01/10/2014 Tests @ DL |
Kept largely the same settings at the entry https://elog.ph.ed.ac.uk/AIDA/4
Same ASIC settings
Emco used to provide HV
HV+ --> nnaida11 & nnaida12 (p+n strips, -ve pulser input)
HV- --> nnaida13 & nnaida14 (n+n strips, +ve pulser input)
Stat spectra look roughly the same as those included in the above entry.
Now see large peak around ~32k, present in all spectra to some degree. Mostly larger than corresponding pulser peak.
Power cycled several times, reloaded+checked ASIC settings etc., no change. Any ideas? Have I forgotten something?
The ASIC events stats rate is also very high on nnaida11,12,14. 13 is high but not excessively.
Pulser peak shows double peaking on all ASIC channels with individual widths of ~250ch and total width of ~500ch.
Noise peak has width ~50ch. This has reduced somewhat (was ~100s ch) with my last power cycle, but clearly still not gone.
I'll try again in the morning, but if no change will proceed with the shaping time tests with the spectra as they are.
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Attachment 1: nnaida12_stats.png
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Attachment 2: nnaida11_stats.png
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Attachment 3: nnaida13_stats.png
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Attachment 4: nnaida14_stats.png
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Attachment 5: nnaida11_allnoise.png
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Attachment 6: nnaida11_noisefit.png
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Attachment 7: nnaida11_peakfit.png
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Attachment 8: nnaida11_peakfit2.png
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Attachment 9: nnaida12_few.png
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Attachment 10: nnaida13_asic4_noise.png
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Attachment 11: ASICevents_stats.png
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16
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Sun Oct 5 22:42:56 2014 |
Chris Griffin | DL tests on 02/10/14 |
A late entry for the work I carried out on Thursday.
With the Emco box providing the HV, the pulser peak showed double (or triple) peaks. This was not seen with the SY1527 so I thought this would be better for looking at peak widths.
Same ASIC settings my previous entry, and a HV of 200V with leakage current 3.8uA.
I varied the shaping time in each module using the ASIC4 control page as this also changes the hold time automatically. Slow comparitor threshold of 64.
Checked each module and took sample channels from a couple of ASICs in each but made qualitative comparisons with random channels in all ASICs to make sure the chosen ones were representative of the ASIC/module as a whole.
Tables and graphs are included below for nnaida11 and 13. nnaida13 showed a high level of low E noise on some spectra, but the pulser peaks were always well defined single peaks.
nnaida12 showed noises across the full range of many spectra in all ASICs apart from ASIC4. Patrick suggested this module may possibly be suffering and need replacing. A quick scan through some channels showed:
- average peak width @ shaoing time of 0.5us of ~150-180 ch
- same at shaping times of 2.5 and 4.5us. Noise present over full range throughout
My taxi was arriving so I didn't have chance to go through nnaida14 in depth, but a quick scan showed peak widths within ~10-15ch of those seen in nnaida13. |
Attachment 1: ASIC4control-orig.png
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Attachment 2: nnaida11-SY1527spec.png
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Attachment 3: nnaida11-SY1527_2.5stWide.png
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Attachment 4: nnaida11-SY1527_4.5st.png
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Attachment 5: nnaida11-SY1527_4.8.Lpeak3.5st.png
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Attachment 6: nnaida11-Sy1527peakEx.png
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Attachment 7: nnaida11-1.5.L-excel.png
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Attachment 8: nnaida11-3.5.L-excel.png
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Attachment 9: nnaida12-SY1527_FSnoise.png
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Attachment 10: nnaida12-SY1527good.png
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Attachment 11: nnaida13-SY1527peaks.png
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Attachment 12: nnaida13-SY1527_0.5st.png
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Attachment 13: nnaida13-SY1527_1.5st.png
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Attachment 14: nnaida13-SY1527noise.png
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Attachment 15: nnaida13-SY1527peakEx.png
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Attachment 16: nnaida13-SY1527peakEx2.png
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Attachment 17: nnaida14-SY1527_1st.png
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886
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Wed Aug 9 14:40:28 2023 |
Carole, Nic, Jeroen | AIDA HV SUPPLY & PULSER TEST |
Tests with the HV supply (CAEN N1419ET) and Pulse Generator ( BNC PB-5 ) in the detector lab on the crate behind the DEGAS detectors, carried out the 9th August 2023
Both modules were plugged
Test 1: pulse generetor on 2 Hz
- DC, 50 ohm - HV OFF - attachment 1
- DC, 50 ohm - HV OFF, Zoom on the noise - attachment 2
- DC, 50 ohm - HV 50 V, Zoom on the noise - attachment 3
Test 2: HV supply Channel 1 - CORE and 2 - BRAID, pulse generator still on
- AC 1 Mohm - HV OFF - attachment 4
- AC 1 Mohm - HV 50 V - attachment 5
No differences were observed between crate OFF, HV OFF and HV 50 V. An important periodic noise (green on the pictures) was observed and was significantly smaller when unpluging the HV module from the crate. The thickness of the baseline noise seems to be comparable to entry 882, attachment 33-35.
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Attachment 1: AIDA_PulserTest_0908_FullPulse.png
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Attachment 2: AIDA_PulserTest_09.08_5mV_10us_HVOFF.png
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Attachment 3: AIDA_PulserTest_0908_10mV_10us_50HV.png
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Attachment 4: HV_0V_090823_1500_wPulser.png
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Attachment 5: HV_-50V_090823_1500_wPulser.png
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190
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Fri Apr 29 11:11:20 2016 |
CG,PV,TD | Friday 29 April |
MSL type BB18 serial # 2977-20 bias +100V I_L +12.0uA T=23 deg C
(biased by nnaida # 3 & 5 )
DSSSD - AIDA adaptor PCB cabling
4 off LH Coupler (Kapton PCB, 5cm), 2x 34-way Samtec ribbon cable (62cm p+n, 53cm n+n),
RH coupler(Kapton PCB, 10cm)
+ 3M 1245 1.4mil copper foil screen ribbon cables (i.e. not RH & LH couplers)
+ drain wires -> gold-plated Lemo-00 test input connectors
to FEE64s in 4x FEE module crates
Snout drain wire to FEE module Cu block
nnaida 3 & 8 AIDA adaptor PCB rev C
nnaida 5 & 9 AIDA adaptor PCB rev C (LK1 fitted)
ground links LK3 & LK7 fitted to nnaida3, 5, 8, & 9 AIDA adaptor PCBs
*** Note added 11.58 sat 30 Apr 2016
Detector bias cable to nnaida3 & 5 adaptor PCBs *but* LK1 fitted to nnaida9 *not* nnaida5.
This has been set this way since start of current series of tests Wed 27 April. Connecting
via a different adaptor PCB to that connected to the CAEN N1419 bias supply causes significant
noise issues presumably due to high resistance path via 2x adaptor PCB to DSSSD cables
and the DSSSD bias bus line on the DSSSD.
Heavy duty copper cable connects copper front end frames of FEE modules
Nitto 5011N conductive gasket between FEE module and front end frames
Standard ASIC settings
nnaida 3 & 8 - negative input
nnaida 5 & 9 - positive input
Pulser BNC PB-4
Fall time 1.0ms
Rate c.100Hz
Delay min
Amplitude 50,000
Polarity -
Pulse top Tail
Atten 10x
+ polarity via EG&G Ortec 433A Sum & Invert Amplifier
Pulser peak widths broad, structured, non gaussian c. 200ch FWHM
attachments 1-4 ASIC # 1 waveforms for each acqserver with all acqservers connected to same PSU
attachments 5-6 for comparison, from yesterday, with acqservers from two different PSUs - note
absence of HF noise in attachments 1-4 cf. attachments 5-6. |
Attachment 1: nnaida3_-_nnaida3_5_8_9_to_1xPSU.png
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Attachment 2: nnaida5_-_nnaida3_5_8_9_to_1xPSU.png
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Attachment 3: nnaida8_-_nnaida3_5_8_9_to_1xPSU.png
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Attachment 4: nnaida9_-_nnaid3_5_8_9_to_1xPSU.png
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Attachment 5: nnaida8_wav_1DSSD_4crates_400chFWHM.png
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Attachment 6: nnaida5_wav_1DSSD_4crates_250chFWHM.png
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191
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Sat Apr 30 07:46:47 2016 |
CG,PV,TD | Saturday 30 April 2016 |
MSL type BB18 serial # 2977-20 bias +100V I_L +12.45uA T=23 deg C
(biased by nnaida # 3 & 5 )
DSSSD - AIDA adaptor PCB cabling
4 off LH Coupler (Kapton PCB, 5cm), 2x 34-way Samtec ribbon cable (62cm p+n, 53cm n+n),
RH coupler(Kapton PCB, 10cm)
+ 3M 1245 1.4mil copper foil screen ribbon cables (i.e. not RH & LH couplers)
+ drain wires -> gold-plated Lemo-00 test input connectors
to FEE64s in 4x FEE module crates
3M 1245-wrapped cables enclosed by polyethyelene bags (supplied to deliver 90cm Printech Kapton PCBs)
to ensure no electrical contact with snout, DSSSD mounting tubes, snout base etc
Snout drain wire to FEE module Cu block
nnaida 3 & 8 AIDA adaptor PCB rev C
nnaida 5 & 9 AIDA adaptor PCB rev C (LK1 fitted)
ground links LK3 & LK7 *not* fitted to nnaida3, 5, 8, & 9 AIDA adaptor PCBs
LK1 fitted to nnaida5 ( cf. https://elog.ph.ed.ac.uk/AIDA/190 )
Heavy duty copper cable connects copper front end frames of FEE modules
Nitto 5011N conductive gasket between FEE module and front end frames
Standard ASIC settings
nnaida 3 & 8 - negative input
nnaida 5 & 9 - positive input
Pulser BNC PB-4
Fall time 1.0ms
Rate c.100Hz
Delay min
Amplitude 50,000
Polarity -
Pulse top Tail
Atten 10x
+ polarity via EG&G Ortec 433A Sum & Invert Amplifier
Standard ASIC settings
Shaping time 8us
LEC/MEC Slow com 32 (dec)
Fast com 32 (dec)
HEC Fast com 2(dec)
Attachments 1-4 ASIC #1 waveforms from each FEE64
5-8 ASIC #2 spectra + 2.0.L pulser peak width
Pulser peak widths (ch FWHM) versus shaping time ( spectrum 2.4.L )
tau nnaida3 nnaida5 nnaida8 nnaida9
8 68 60 70 62
4 83 49 88 48
2 100 47 109 43
1 172 60 165 42
0.5 380 86 309 48
Note: n+n ohmic strips spectra > 100 ch FWHM display non-gaussian peaks/double peaking
15.45 Attempted to increase detector bias from +100V to +150V
Leakage current increased ~0.5uA/V for bias > 115V
Detector bias supply trips (20uA) at +120V
Remain at detector bias +100V
16.17 Switch polarity of detector bias from + to -
Move LK1 from nnaida5 to nnaida3
tau nnaida3 nnaida5 nnaida8 nnaida9
8 61 64 65 61
n+n ohmic strips ~10% improvement, p+n junction strips no significant change
16.30 Fit LK3/LK7 jumpers to connect adaptor PCB ground to detector PCB ground
tau nnaida3 nnaida5 nnaida8 nnaida9
8 61 64 62 60
No significant change to cf. previous test
18.30 Install second DSSSD
Upstream 3058-6 bias +100V I_L 4.15uA
Downstream 2977-20 bias +100V I_L 11.8uA
+ 207Bi source ~3cm upstream of 3058-6
Standard ASIC settings
shaping time 6us
slow comp 8(dec)
HEC fast comp 2(dec)
LEC/MEC fast comp 16(dec)
Pulser peak widths ~60 ch FWHM per previous tests today
Discriminator masks TBD
22.27 R2 to disk (directory /data20/TapeData/May2016)
MERGE data links 2-9
Run data to disk overnight. Add two more DSSSDs tomorrow.
09.21 R2 stopped |
Attachment 1: nnaida3_wav_nnaida5Lk1_cableBags.png
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Attachment 2: nnaida5_wav_nnaida5Lk1_cableBags.png
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Attachment 3: nnaida8_wav_nnaida5Lk1_cableBags.png
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Attachment 4: nnaida9_wav_nnaida5Lk1_cableBags.png
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Attachment 5: nnaida3_spec_nnaida5Lk1_cableBags.png
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Attachment 6: nnaida5_spec_nnaida5Lk1_cableBags.png
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Attachment 7: nnaida8_spec_Lk1nnaida5_cablesBags.png
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Attachment 8: nnaida9_spec_nnaida5Lk1_cableBags.png
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Attachment 9: 1.png
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Attachment 10: 2.png
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Attachment 11: 3.png
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193
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Sun May 1 07:59:08 2016 |
CG,PV,TD | AIDA Detector Configuration |
UPSTREAM
Detector Serial Operating CAEN N1519 CAEN N1519 Bias FEE64 Bias Config
# # Bias (V) Addr # channel # Cable Core Braid
1 3058-2 +100 0 0 1 nnaida25, 27, 30 & 32 nnaida27 nnaida29 (LK5)
2 3058-3 +100 0 1 2 nnaida18, 20, 22 & 23 nnaida20 nnaida22 (LK1)
3 3058-4 +100 0 2 3 nnaida17, 19, 21 & 24 nnaida19 nnaida21 (LK5)
4 3058-5 +100 0 3 4 nnaida10, 12, 14 & 15 nnaida12 nnaida14 (LK1)
5 3058-6 +100 1 0 5 nnaida9, 11, 13 & 16 nnaida11 nnaida13 (LK5)
6 3058-7 +100 1 1 6 nnaida2, 4, 6 & 7 nnaida4 nnaida6 (LK1)
7 2977-15 +100 1 2 7 nnaida1, 3, 5 & 8 nnaida3 nnaida5 (LK5)
8 1 3 8
DOWNSTREAM
Notes
_____
MSL type BB18 PCB ground links (LK3 & LK7) not fitted
To be checked |
197
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Mon May 2 12:13:25 2016 |
CG,PV,TD | Monday 2 May 2016 |
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Attachment 1: 10.png
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Attachment 2: 11.png
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Attachment 3: 12.png
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Attachment 4: 13.png
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Attachment 5: 14.png
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Attachment 6: 15.png
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Attachment 7: 16.png
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Attachment 8: 17.png
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Attachment 9: 18.png
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Attachment 10: 19.png
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Attachment 11: 20.png
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Attachment 12: 21.png
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Attachment 13: 22.png
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Attachment 14: 23.png
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Attachment 15: 24.png
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Attachment 16: 25.png
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Attachment 17: 30.png
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Attachment 18: 31.png
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Attachment 19: 32.png
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Attachment 20: 33.png
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Attachment 21: 34.png
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Attachment 22: 35.png
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213
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Thu May 5 11:10:36 2016 |
CG,PV,TD | Thursday 5 May 2016 |
Detector configuration - see https://elog.ph.ed.ac.uk/AIDA/193
Ribbon cable to nnaida19 FEE adaptor PCB disconnected due to noise issues
associated with nnaida19 or crate slot or power/timestamp/network cabling
to nnaida19 - to be investigated May 22-
207Bi source ~3cm upstream of DSSSD #1
rate and hit rate spectra for all FEE64s - see attachments 1-4
example ADC spectra for all FEE64s - attachment 5 p+n strips, attachment 6 n+n strips
Default ASIC settings, shaping time 8us (which may, or may not, be optimum - to be
investigated May 22- )
p+n junction strips n+n ohmic strips
FEE64 Pulser peak width FEE64 Pulser peak width
(ch FWHM) (ch FWHM)
1 108 3 88
2 64 4 84
5 112 7 76
6 - 8 85
9 75 11 122
10 82 12 98
13 84 15 127
14 99 16 115
17 77 19 ?
18 69 20 100
21 77 23 89
22 91 24 84
25 80 27 138
26 14 28 16 } not connected to DSSSD
29 17 31 17 }
30 130 32 111
DSSSD bias voltages and leakage currents - attachments 7-8
All bias voltages +100V cf. depletion ~70V for 3058 sequence (MSL type BB18)
Additional bias may be helpful (to be investigated May 22-) |
Attachment 1: 600.png
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Attachment 2: 601.png
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Attachment 3: 602.png
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Attachment 4: 603.png
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Attachment 5: 610.png
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Attachment 6: 611.png
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Attachment 7: 620.png
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Attachment 8: 621.png
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59
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Mon Apr 20 09:07:59 2015 |
CG, TD, Patrick Coleman-Smith | Progress 20th April + RPi procedure + reply |
Quote: |
20/04/15
1200: Complete all points on first part of check list, except checking the PSU voltages.
System now in powered and has all network/HDMI cables attached.
1300: Connect RPi to power switch but when powered on it didn't find the switch. A reliable procedure to start seems to be...
- connect USB power switch to RPI, make sure serial cable is disconnected from hub
- power up RPi and power switch
- check connection using dmesg, should see ...FT232RL for USB power switch on USB0
- check connection from aidas1 by pinging RPi inet address 10.1.1.251
- if good, Rly16 page should work from aidas1
- connect serial cable, open PuTTY session, select AIDA console settings, open
- should assign serial cable as USB1 an allow use of both the power switch and FEE console.
Currently this all works, we can control the power switch both from the RPi and aidas1, and see the FEE console via PuTTY session.
1400: Powered on system and tried to set up DAQ but received error (attachment 1) when doing the initial system reset in Run Control.
DAQ still usable for spectrum/temperature viewing, and all FEEs can be accessed to check ASIC control, but it seems timestamping will not be correct.
Tried to perform manual ReSync from master timestamp window and received similar error (attachment 2).
1430: nnaida8 running quite hot (ASIC temp ~65oC) and ASIC temp on nnaida7+15 read as 0.00oC. Otherwise, from pulser/stats data, both seem to be working correctly.
Unplugged power cable for nnaida7+8 at PSU end.
1600: Could timestamping issue originate from MACBs?
In rebuilding AIDA MACB -> FEE cabling redone. Should it follow a particular pattern/tree?
Current tree structure looks like (with MACB numbering going 1->11 L->R as you look at it):
MACB1(setting: 0) ------- out 1: MACB2 (setting: 2) ---------- out 1: MACB3 (setting: 2) -> nnaida3+4, 11+12
---------- out 2: MACB4 (setting: 3) -> nnaida19+20, 27+28
---------- out 3: MACB5 (setting: 3) -> nniada1+2, 9+10
---------- out 4: MACB6 (setting: 3) -> nnaida17+18, 25+26
--------- out 2: MACB7 (setting: 3) ---------- out 1: MACB8 (setting: 3) -> nnaida21+22, 29+30
---------- out 2: MACB9 (setting: 3) -> nnaida7+8, 15+16
---------- out 3: MACB10 (setting: 3) -> nnaida5+6, 13+14 -----> nnaida5 is the master and this comes from output2.
---------- out 4: MACB11 (setting: 3) -> nnaida23+24, 31+32
Patrick - Is this set up OK? Do certain FEEs need to receive the MACB signal from certain MACBs or just all at the same point in the tree?
Also, MACBs 2+3 are on setting 2 on the dial, whereas the others (except MACB1, the 'grandparent') are set to 3. It seems like a hard thing to change accidentally so are they supposed to be like this or should they all be on the same setting?
1630: Voltages to nnaida7+8 OK at PSU output (+6V, +6V, +6V, -6.5V, +8V). Issue with contact to cooling rack?
With pulser input to all FEEs, only see pulser data in spectra for n-side (nnaida3+4, 7+8, 11+12, 15+16) FEEs. Other FEEs all show zero statistics.
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The MACB system of clock and SYNC pulse distribution does have to follow some rules.
The Master needs to be in a very particular place. The rest are less important as long as they are all at the same level in the tree.
In the tree you report above and using the numbering you report. The Master should be in MACB3:out1.
The settings you have shown are correct if the Master is placed correctly ...
I will input a separate Elog entry detailing the settings for the MACB and the rules for the tree.
Regarding nnaida7+8. I agree the issue to tackle first is the cooling plate contact to the module. Where do they feature in the layout ?
Is the plate tightened up correctly ?
Regarding the P side FEE64s ... sorry about this ... but is the P pulser working ... well i did have to ask ;-)
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60
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Mon Apr 20 09:38:15 2015 |
CG, TD, Patrick Coleman-Smith | Progress 20th April + RPi procedure + reply |
Quote: |
Quote: |
20/04/15
1200: Complete all points on first part of check list, except checking the PSU voltages.
System now in powered and has all network/HDMI cables attached.
1300: Connect RPi to power switch but when powered on it didn't find the switch. A reliable procedure to start seems to be...
- connect USB power switch to RPI, make sure serial cable is disconnected from hub
- power up RPi and power switch
- check connection using dmesg, should see ...FT232RL for USB power switch on USB0
- check connection from aidas1 by pinging RPi inet address 10.1.1.251
- if good, Rly16 page should work from aidas1
- connect serial cable, open PuTTY session, select AIDA console settings, open
- should assign serial cable as USB1 an allow use of both the power switch and FEE console.
Currently this all works, we can control the power switch both from the RPi and aidas1, and see the FEE console via PuTTY session.
1400: Powered on system and tried to set up DAQ but received error (attachment 1) when doing the initial system reset in Run Control.
DAQ still usable for spectrum/temperature viewing, and all FEEs can be accessed to check ASIC control, but it seems timestamping will not be correct.
Tried to perform manual ReSync from master timestamp window and received similar error (attachment 2).
1430: nnaida8 running quite hot (ASIC temp ~65oC) and ASIC temp on nnaida7+15 read as 0.00oC. Otherwise, from pulser/stats data, both seem to be working correctly.
Unplugged power cable for nnaida7+8 at PSU end.
1600: Could timestamping issue originate from MACBs?
In rebuilding AIDA MACB - > FEE cabling redone. Should it follow a particular pattern/tree?
Current tree structure looks like (with MACB numbering going 1->11 L->R as you look at it):
MACB1 (setting: 0) ------- out 1: MACB2 (setting: 2) ---------- out 1: MACB3 (setting: 2) -> nnaida3+4, 11+12
&nb sp; &nb sp; ---------- out 2: MACB4 (setting: 3) -> nnaida19+20, 27+28
&nb sp; &nb sp; ---------- out 3: MACB5 (setting: 3) -> nniada1+2, 9+10
&nb sp; &nb sp; ---------- out 4: MACB6 (setting: 3) -> nnaida17+18, 25+26
&nb sp; --------- out 2: MACB7 (setting: 3) ---------- out 1: MACB8 (setting: 3) -> nnaida21+22, 29+30
&nb sp; &nb sp; ---------- out 2: MACB9 (setting: 3) -> nnaida7+8, 15+16
&nb sp; &nb sp; ---------- out 3: MACB10 (setting: 3) -> nnaida5+6, 13+14 -----> nnaida5 is the master and this comes from output2.
&nb sp; &nb sp; ---------- out 4: MACB11 (setting: 3) -> nnaida23+24, 31+32
Patrick - Is this set up OK? Do certain FEEs need to receive the MACB signal from certain MACBs or just all at the same point in the tree?
Also, MACBs 2+3 are on setting 2 on the dial, whereas the others (except MACB1, the 'grandparent') are set to 3. It seems like a hard thing to change accidentally so are they supposed to be like this or should they all be on the same setting?
1630: Voltages to nnaida7+8 OK at PSU output (+6V, +6V, +6V, -6.5V, +8V). Issue with contact to cooling rack?
With pulser input to all FEEs, only see pulser data in spectra for n-side (nnaida3+4, 7+8, 11+12, 15+16) FEEs. Other FEEs all show zero statistics.
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The MACB system of clock and SYNC pulse distribution does have to follow some rules.
The Master needs to be in a very particular place. The rest are less important as long as they are all at the same level in the tree.
In the tree you report above and using the numbering you report. The Master should be in MACB3:out1.
The settings you have shown are correct if the Master is placed correctly ...
I will input a separate Elog entry detailing the settings for the MACB and the rules for the tree.
Thanks
Regarding nnaida7+8. I agree the issue to tackle first is the cooling plate contact to the module. Where do they feature in the layout ?
Is the plate tightened up correctly ?
As far as I am aware this module/crate has not recently been opened so the 'contact' should be as good (or bad) as it ever was.
But it would, of course, bear checking.
Regarding the P side FEE64s ... sorry about this ... but is the P pulser working ... well i did have to ask ;-
According to a DSO the positive and negative pulser inputs and cabling are OK
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Mon Apr 20 09:45:38 2015 |
CG, TD, Patrick Coleman-Smith | Progress 20th April + RPi procedure + reply ++ |
Quote: |
Quote: |
Quote: |
20/04/15
1200: Complete all points on first part of check list, except checking the PSU voltages.
System now in powered and has all network/HDMI cables attached.
1300: Connect RPi to power switch but when powered on it didn't find the switch. A reliable procedure to start seems to be...
- connect USB power switch to RPI, make sure serial cable is disconnected from hub
- power up RPi and power switch
- check connection using dmesg, should see ...FT232RL for USB power switch on USB0
- check connection from aidas1 by pinging RPi inet address 10.1.1.251
- if good, Rly16 page should work from aidas1
- connect serial cable, open PuTTY session, select AIDA console settings, open
- should assign serial cable as USB1 an allow use of both the power switch and FEE console.
Currently this all works, we can control the power switch both from the RPi and aidas1, and see the FEE console via PuTTY session.
1400: Powered on system and tried to set up DAQ but received error (attachment 1) when doing the initial system reset in Run Control.
DAQ still usable for spectrum/temperature viewing, and all FEEs can be accessed to check ASIC control, but it seems timestamping will not be correct.
Tried to perform manual ReSync from master timestamp window and received similar error (attachment 2).
1430: nnaida8 running quite hot (ASIC temp ~65oC) and ASIC temp on nnaida7+15 read as 0.00oC. Otherwise, from pulser/stats data, both seem to be working correctly.
Unplugged power cable for nnaida7+8 at PSU end.
1600: Could timestamping issue originate from MACBs?
In rebuilding AIDA MACB - > FEE cabling redone. Should it follow a particular pattern/tree?
Current tree structure looks like (with MACB numbering going 1->11 L->R as you look at it):
MACB1 (setting: 0) ------- out 1: MACB2 (setting: 2) ---------- out 1: MACB3 (setting: 2) -> nnaida3+4, 11+12
&nb sp; &nb sp; ---------- out 2: MACB4 (setting: 3) -> nnaida19+20, 27+28
&nb sp; &nb sp; ---------- out 3: MACB5 (setting: 3) -> nniada1+2, 9+10
&nb sp; &nb sp; ---------- out 4: MACB6 (setting: 3) -> nnaida17+18, 25+26
&nb sp; --------- out 2: MACB7 (setting: 3) ---------- out 1: MACB8 (setting: 3) -> nnaida21+22, 29+30
&nb sp; &nb sp; ---------- out 2: MACB9 (setting: 3) -> nnaida7+8, 15+16
&nb sp; &nb sp; ---------- out 3: MACB10 (setting: 3) -> nnaida5+6, 13+14 -----> nnaida5 is the master and this comes from output2.
&nb sp; &nb sp; ---------- out 4: MACB11 (setting: 3) -> nnaida23+24, 31+32
Patrick - Is this set up OK? Do certain FEEs need to receive the MACB signal from certain MACBs or just all at the same point in the tree?
Also, MACBs 2+3 are on setting 2 on the dial, whereas the others (except MACB1, the 'grandparent') are set to 3. It seems like a hard thing to change accidentally so are they supposed to be like this or should they all be on the same setting?
1630: Voltages to nnaida7+8 OK at PSU output (+6V, +6V, +6V, -6.5V, +8V). Issue with contact to cooling rack?
With pulser input to all FEEs, only see pulser data in spectra for n-side (nnaida3+4, 7+8, 11+12, 15+16) FEEs. Other FEEs all show zero statistics.
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The MACB system of clock and SYNC pulse distribution does have to follow some rules.
The Master needs to be in a very particular place. The rest are less important as long as they are all at the same level in the tree.
In the tree you report above and using the numbering you report. The Master should be in MACB3:out1.
The settings you have shown are correct if the Master is placed correctly ...
I will input a separate Elog entry detailing the settings for the MACB and the rules for the tree.
Thanks
Regarding nnaida7+8. I agree the issue to tackle first is the cooling plate contact to the module. Where do they feature in the layout ?
Is the plate tightened up correctly ?
As far as I am aware this module/crate has not recently been opened so the 'contact' should be as good (or bad) as it ever was.
But it would, of course, bear checking.
Regarding the P side FEE64s ... sorry about this ... but is the P pulser working ... well i did have to ask ;-
According to a DSO the positive and negative pulser inputs and cabling are OK
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Regarding the P side problem.
What is the result if you change one of the N-Side FEEs to use the P-side pulser and vice-versa ?
Regarding the temperature problem.
Which position are the problem modules in ? |
120
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Sat Nov 14 20:19:43 2015 |
CG, TD, PJCS | 13 Nov 2015 - new Kapton cable tests at DL |
Quote: |
Powered system up with 4 bare 45cm kaptons connected and nothing seems to have changed from where we left last night
Waveforms in nnaida11 look good and peak widths in nnaida11 1.8.L and 1.10.L are ~70ch.
Turned off flash ADCs for all FEEs by setting Q8_transfer.vhd: 0xa00, offset 0x00, to 0 to assess any affect they may play in the observed noise
no obvious change in peak widths for nnaida11
turned all back on by resetting value of offset 0x00 to 1
Measured RMS deviation of waveform baseline for nnaida11 with 45cm unshielded kapton connected by sampling waveform every 10 samples over 100 samples, i.e. every 200ns for 2us.
1.4.W - mean: 8612.9 st. dev.: 20.5
1.6.W - mean: 8548.9 st. dev.: 16.6
1.8.W - mean: 8900.8 st. dev.: 16.2
1.10.W - mean: 8744.5 st. dev.: 15.0
Removed kapton to check intrinsic RMS deviation of pre-amp using the same method
1.4.W - mean: 8666.8 st. dev.: 4.7
1.6.W - mean: 8586.6 st. dev.: 2.0
1.8.W - mean: 8918.7 st. dev.: 3.2
1.10.W - mean: 8782.3 st. dev.: 4.2
These results are consistent with the pulser peak widths observed with/without Kapton PCBs attached
Make a makeshift screening plate for the adapter PCBs using the Cu tape -> widths in nnaida11 all slightly worse but still comparable.
Connected detector using 4 45cm kaptons (gnd via nnaida13) and baised via nnaida12+13 to +200V with a leakage current of 5.16uA (Room temp 24.2oC)
Initially observed very noisy waveforms but grounding adapter PCBs together improved the noise slightly but not to an acceptable level (see attachment 2+3).
Measure the peak width as a function of shaping time:
t_shape: 0.5 | 1.0 | 2.0 | 4.0 | 8.0
FWHM (ch): 308 | 352 | 345 | 252 | 130
Throughout, the peaks were non-Gaussian and double peaked with single peak widths ~50-70ch.
Pickup effect rather than white noise?
Shielded kapton to nnaida11 with Cu tape and found noise to decrease slightly when grounded to LEMO connector on adapter PCB - bursts reduced in amplitude but persistent periodic noise remained (see attachments 4+5).
Changed grounding around (adapters to NIM crate, adapters to detector box etc) and observed no noticeable difference.
However, removing jumpers grounding PCBs to FEE cards and the grounding between the adapter PCBs makes the noise worse.
Shielded 3 more 45cm kaptons and connected detector -> no leakage current.
Found several pins on 2 kaptons to be broken. Will get these fixed in Edinburgh for use next week.
Reconnected old kaptons and system is as expected - slower rise time in waveforms but reasonable levels of noise and expected peak widths (see attachment 6).
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To power down the ADCs the register to be loaded with 0xFF is in the "Local Registers" window.
What you did was to disable the readout of the ADCs which doesn't change the level of activity or reduce the power.
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126
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Wed Nov 25 19:24:39 2015 |
CG, TD, PJCS | New Kapton cable tests at DL |
Powered system on and biased to +200V at room temp of 22.4oC. Leakage current of 3.37uA.
Waveforms very noisy and spectra dominated by low E noise. Upon taking a close look at front end found one of the kaptons to have broken a connection. Swapped it out for a spare.
Returned to same situation as last week. Peaks all have a shoulder at t_shape of 8us, but main peak has width ~80ch. Shorter shaping times lead to double peaking.
Removed FEEs from crate and properly seated adapter PCBs on Cu mounting block, with washers between plated part of PCB and allen screw.
- <0.4 ohm impedance betwee Cu mount block and washer/screw but ~20 ohms between screw and LEMO connector => 20 ohms between Cu mounting block and LEMO connectors
- plating around screw holes doesn't go anywhere.
Confirmed LEMOs are connected to ASIC ground (as they should be) on the Cu mezzanine block with <0.2 ohm impedance between mezzanine Cu and LEMO connectors.
With adapter PCBs removed, Cu mezzanine blocks of separate modules still have impedance < 0.3 ohm between them. How/why?
- found out MACB cables, power cables and network cables all connect the grounds of each FEE card/module. Was this expected? Does this cause us problems?
Swapped non-functioning nnaida12 for the former nnaida11 from the module featuring the other broken nnaida12 - all seems to work, although no waveforms are produced.
Very low impedance between ASIC grounds of FEE cards in same module.
To obtain a better ground connection between the ASIC grounds of separate modules, connected a thick braid to Cu mezzanine block of each. Operating at limit of multimeter so no noticeable difference in impedance. But...
With mezzanines connected and thick braid connecting HV and pulser at LEMO connectors, see the best waveforms so far; very little noise, some transients (attachments 1+2).
However, in nnaida14 waveform does not get back to baseline properly after a pulser event (attachments 2+3).
Despite very clean waveforms, still see double-peaking in spectra, although peak widths are fairly low (attachment 6).
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Attachment 1: nnaida11_wav_mezzConnectedPlusThickBraid.png
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Attachment 2: nnaida14_wav_mezzConnectedPlusThickBraid.png
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Attachment 3: nnaida14_wav_resetDiff.png
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Attachment 4: nnaida11_wav.png
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Attachment 5: nnaida1_wav_multi.png
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Attachment 6: nnaida11_spec4us.png
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Wed Jan 6 16:06:32 2016 |
CG, TD, PJCS | Report: Low - RPi power cable can't be fully inserted due to case conflict - solved |
Quote: |
The RPi power cable cannot sit fully in the connector, and the lock pins can't engage, because the case gets in the way of the plastic around the end.
As a result we have knocked it out a couple of times and lost power to the system.
Can this be modified or can we get a new case/cable that resolves this issue?
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The case has been changed for one that doesn't allow the power cable to be easily extracted. |
423
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Sat Nov 5 01:55:15 2016 |
CG, TD, OH | Saturday 5th November |
10.55 DAQ found to have stopped at 06:47 during LN fill cycle.
10:57 Screen shots of system after stop
11.20 R122 started.
System check screen shots attached at 11:08
18.20 System been running stably all day. Leakage currents attachments 14+15.
LN2 fill cycle shortly, anticipate DAQ stop.
19.16 DAQ stopped.
Closed file R122.
19.37 Temp 25.3 DP 6.1 Hum 31.1
Added 2 extra stacks of lead bricks to protect AIDA. Now ~15cm of lead (Attachment 17)
23.30 DSSSD bias & leakage currents OK - see attachments 18-19
FEE74 temperatures OK - see attachment 20
23.54 DAQ starts (R124)
Merge rate 1.8M items/s, c. 13Mb/s to disk c. x2 earlier rates
Dominated by significantly higher rates from DSSSD#1
FEE64 #17 ASIC 2*L pulser peak widths ~300 ch FWHM
Needs to be investigated at next entry opportunity |
Attachment 1: temp_1057.png
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Attachment 2: FEE64_Memory_1057.png
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Attachment 3: SYNC_puls_1057.png
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Attachment 4: asic_SYNC_1057.png
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Attachment 5: asic_timestamp_1057.png
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Attachment 6: adc_calibration_1057.png
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Attachment 7: clock_status.png
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Attachment 8: bias2_10_57.png
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Attachment 9: bias1_10_57.png
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Attachment 10: feee_mem_1108.png
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Attachment 11: sync_pulses_1008.png
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Attachment 12: sync_baseline_1108.png
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Attachment 13: adc_calib_1108.png
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Attachment 14: clock_status_1108.png
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Attachment 15: bias_1820.png
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Attachment 16: bias2_1820.png
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Attachment 17: 2016-11-05_19.31.44.jpg
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Attachment 18: 1.png
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Attachment 19: 2.png
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Attachment 20: 3.png
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436
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Tue Nov 8 15:10:16 2016 |
CG, TD, DK, OH | NP1412 R5 R6 |
00.15 Setting changed to 71,72,73Ni. All variable degraders in.
Will remove while watching rates to settle on degrader setting.
F5 CH2 in. F7 CH2 out. F11 C target in.
F11 plastic rate 1.2kHz.
R5 started.
00.30 Cut F2 momentum slit. F11 plastic rate down to ~400cps.
00.34 Increased primary beam intensity by x2.
F11 plastic rate increased to ~800cps.
This setting should run until the beam change ~03.00.
00.47 R6 started.
All degraders gradually removed but implant rate in DSSD1 only ~10s Hz.
01.03 71,72,73Ni beam stopped for tuning to next setting.
R6 stopped.
Leakage currents attachments 1+2 |
Attachment 1: bias1.png
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Attachment 2: bias2.png
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291
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Tue Jun 7 19:19:34 2016 |
CG, TD, DK, AE | Wednesday 8th June |
(4 mm Al mask was put upstream of AIDA near 20:20 on 7 June)
01.15 Run R1219 started on neutron rich setting.
Temps ok. Leakage currents ok.
Plate with holes in front of AIDA , after F11 plastic. F11 plastic count rate ~700cps.
Keeps getting 'Attempting resychronisation' message in merger terminal window.
driver 0 10205 consuming almost 100% of CPU. Merger ~20% and data links ~1%
See attachments 1-4
02.15 Run R1220 n-rich setting (BigRIPS run 1218, EURICA off)
EURICA team retires for the night and cannot get it up and running
Biases and leak shown as attachments 5-6
Merger info is shown in attachments 7-9
CPU Load in attachment 10
Timestamps against the ADCs and also SYNCS, respectively, attachments 11 and 12
3:31: Run stopped for the operator to tune the beam
F11 plastic rate was 700 cps (~heavy ion injection rate)
3:43 Run R1221 n-rich setting (BigRIPS 1219, no EURICA)
4 mm Al mask was removed.
Pause calls vs. Timestamp is attachment 13
Merger screenshots are shown as attachments 14-16
F11 plastic rate is 850 or 900 cps after retune
ADC v Timestamp is shown as attachment 17. It can be seen the rate was roughly constant before the operators stopped (corresponding to a long gap of no hits, but now we go up and down quite a lot in a rather ugly way
CPU stats (driver to write to HDD in green, merger in red) as attachment 18
At the time of ~90 in attachment 18, the linkers start to consume all available CPU resources, shown as attachment 19
04:35 Run R1222 n-rich setting (BigRIPS 1219 / 1220)
Ask the operators to reduce the beam intensity by "1/2" -> F11 plastic rate goes from 850 cps to 170 cps, so more like 1/4 effectively
Merger stats are shown as attachments 20, 21, 22.
nnaida1 and nnaida24 seemed to often show pauses (among other ones)
trying to understand what's going on with the display in Midas, because it has looped around to time zero and is putting new data on to the old data...?
It seems this condition is much better than before, though
05:33 stop the run
05:38 R R1223 n-rich setting (BigRIPS 1221)
Ask the operators to resume the previous beam intensity. (Now like 600 to 800 cps at the F11 plastic)
attachment 23 shows the beam coming on near time zero. within <100 seconds, the driver has to fight with many link64 instances and cannot operate correctly
we understood how to clear the midas histograms so that we can make sense of things. attachment 24 is ADC, and attachment 25 is pause.
you can see some data come smoothly until the system locks down
06.11 R1223 stopped.
06.30 Started run R1224.
Moved Pb bricks downstream of F11 plastic inwards, from a separation of 15cm, to 4cm in an effort to reduce rate in AIDA.
F11 plastic rate ~900cps.
No change to vis scalar rates and data still being dropped.
06.45 Stopped run R1224.
MIDAS plot of ADC vs Timestamp (attachment 26) shows characteristic behaviour.
Upon writing to disk, for the first minute or so link64 processes consume minimal CPU power. But then very quickly they ramp up consumption and ultimately choke the merger (it seems).
This is reflected in the ADC v TS plot. Continuous ADC data for first ~1min.
06.54 Moved Pb bricks to separation of 2cm. Started run R1225.
AIDA vis scalar rates reduced slightly, but no change to CPU usage and usual happens - data lost, link64 CPU usage spikes and chokes merger (seemingly).
F11 plastic rate ~900cps.
07.00 Run R1225 stopped.
SYNCs stopped being produced. Lost contact with nnaida1.
07.25 Pb bricks moved to 1cm apart. Run R1226 started.
No change to CPU usage (link64 still hogging everything). MIDAS online monitor lost in power cycle so cant view in real-time, but anticipate same outcome.
Sopped producing SYNCs 07.39. Run 1226 stopped.
08.20 Some trouble restarting DAQ and merger.
As nnaida19 has lost the 'H' for histogramming on the run control page, nnaida21 has now lost the 'X' for data transfer (see attachment 27).
Removed nnaida21 from merger and normal state of play resumed.
4mm holey plate + the one attached to it we installed dowstream of F11 plastic.
08.50 Run R1227 started.
CPU usage by link64 ~1% and driver ~70%, much more reasonable. When reloading merger web page, channels flash between bright green and olive. Good.
09.09 Changed to reference mass setting. Run R1227 stopped.
09.12 Run R1228 started on reference setting with holey plate still in place.
R1228 stopped 10.32 (for B2F/F11 entry)
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Attachment 1: merge_rate_resync.png
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Attachment 2: merge_resync.png
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Attachment 3: tape_resync.png
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Attachment 4: disk_driver_CPU_usage.png
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Attachment 5: bias1_R1220_0806-03.10.png
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Attachment 6: bias2_R1220_0806-03.10.png
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Attachment 7: R1220_MergeControl_0806-03.12.png
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Attachment 8: MergerLinkRates_R1220_0806-03.13.png
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Attachment 9: MergerStats_R1220_08-6-03.13.png
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Attachment 10: cpuload_R1220_0806-03.16.png
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Attachment 11: ADCvTimestamp_R1220_0806-03.17.png
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Attachment 12: SYNCSvTimestamp_R1220_0806-03.18.png
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Attachment 13: PauseVTimestamp_R1221_0806_03.51.png
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Attachment 14: MergeControl_R1221_0806_03.50.png
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Attachment 15: MergerStats_R1221_0806_03.50.png
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Attachment 16: MergerRates_R1221_0806_03.49.png
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Attachment 17: ADCvT_R1221_0806_04.02.png
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Attachment 18: CPULoad_R1221_0806_04.06.png
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Attachment 19: TOP_R1221_0806_04.16.png
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Attachment 20: Merger_R1222_0807-04.59.png
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Attachment 21: MergerStats_R1222_0806-05.00.png
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Attachment 22: MergerLink_R1222_0806-04.59.png
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Attachment 23: CPUStat_R1223_0806-05.58.png
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Attachment 24: ADC_v_T_R1223_0806-06.03.png
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Attachment 25: Pause_v_T_R1223_0806-06.04.png
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Attachment 26: ADCvTS_R1224_0639.png
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Attachment 27: nnaida21_noDataXfer.png
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494
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Mon Nov 28 18:07:14 2016 |
CG, TD, AE, DK | Tuesday 29 November |
01:39 : Attachment 26 (R30_70to72) shows a gradual change in the hit pattern for DSSD2 (at the lower left
corner) which may indicate the noise level was increasing.
02.23 BigRIPS data file 1066
03.05 Beam stopped due to problem with LINAC RF.
Stopped at 1GB through R30_90.
Bias and leakage currents ok (attachments 1+2). Temps ok (attachment 3).
03.15 R30 stopped.
03.22 BigRIPS data file 1067
03.24 Beam returned and R31 started.
04.25 BigRIPS data file 1068
05.29 BigRIPS data file 1069
06.26 Stop R31 in anticipation of LN2 fill.
Run stopped at R31_56.
06.31 BigRIPS data file 1070
07.18 R32 started successfully after LN2 fill.
07.24 DAQ crashed. SYNC errors.
R32 closed.
Cannot soft reset. Unable to contact nnaida9+19.
07.33 BigRIPS data file 1071
07.49 R33 started after FEE power cycle.
Running quite fast, but seems to be stable. F11 rate still 30cps.
08.26 /home full.
aidas1> du -sh /home/data/
811G /home/data/
aidas1> du -sh /home/data/*
3.4M /home/data/bkg_r97.root
253G /home/data/NP1306.rootfiles
27G /home/data/NP1512.rootfiles
190G /home/data/npg
311G /home/data/online
2.0G /home/data/R97_0
2.0G /home/data/R97_1
2.0G /home/data/R97_10
2.0G /home/data/R97_11
1.8G /home/data/R97_12
2.0G /home/data/R97_2
2.0G /home/data/R97_3
2.0G /home/data/R97_4
2.0G /home/data/R97_5
2.0G /home/data/R97_6
2.0G /home/data/R97_7
2.0G /home/data/R97_8
2.0G /home/data/R97_9
7.4G /home/data/rootFiles
4.0K /home/data/rsync.sh
4.0K /home/data/rsync.sh~
4.0K /home/data/ttt.txt
08.36 BigRIPS data file 1072
09.16 Beam stopped for stripper foil change.
R33 stopped.
GK, RG and SN will install repaired clover (G7).
09.28 Beam returned and R34 started.
BigRIPS data file 1073
10.32 BigRIPS data file 1074
11.00 DSSSD bias & leakage currents OK - see attachments 4 & 5
FEE64 temperatures OK - see attachment 6
Merge statistics OK - see attachments 7-12
System wide checks OK *except* fails for clock status (bit 2 always set) and ADC calibration - see
attachments 13-14
11.20 Visual scaler - see attachment 15
11.25 Analysis of R30_25 - see attachment 16
11.39 BigRIPS data file 1075
13.11 BigRIPS data file 1076
14.10 11.50-14.10 Spectra Rate, HitRate, 1.8.L, 1.8.H, 1.8.W - see attachments 17-24
1.8.W spectra show some evidence of increased 100kHz noise for nnaida17, 18 & 19
statistics good events - nnaida17, 18 & 19 > 100k data item/s - see attachment 25
14.16 BigRIPS data file 1077
14.54 BigRIPS data file 1078
15.19 BigRIPS data file 1079
16.14 BigRIPS data file 1080
16.16 BigRIPS data file 1081
17.17 BigRIPS data file 1082
18.18 BigRIPS data file 1083
19.03 BigRIPS data file 1084
18.26 DAQ stopped OK (RIBF03R1/R34_137)
Clover HPGe LN2 refill
18.30 Beam off - for primary user calibration & stripper foil change
18.45 Ambient temperature +25.5 deg C, d.p. -5.0 deg C, RH 12.%
DSSSD bias & leakage currents OK - see attachments 27 & 28
FEE64 temperatures OK - see attachment 29
19.03 BigRIPS data file 1084
19.12 Statistics good events - see attachment 30
All FEE64s < 100k data items/s, nnaida17, 18 & 19 < 50k data items/s
Note - nothing has been changed/touched
19.40 Degraders unchanged
(8mm Al) Fixed + ( 1mm W/1mm Al, 0.3mm W/1mm Al) variable
19.46 DAQ starts (RIBF0R1/R35)
19.50 SyncCheck OK
19.51 BRIKEN data file 155
19.53 Statistics - good events - see attachment 31
All FEE64s < 100k data items/s, nnaida17, 18 & 19 < 50k data items/s
Visual scalers - see attachment 32
20.00 BigRIPS data file 1085
20.08 Offline analysis R35_1 - ADc & disc data synchronised - see attachments 33 & 34
20.58 BigRIPS data file 1086
21.15 Rate, HitRate, 1.8.L, 1.8.H, 1.8.W spectra - see attachments 35-42
21.35 Found nnaida17 HEC fast comparator 0x3 *not* 0x2
Corrected and saved ASIC settings etc with new DB key 2016Nov29-21.38.02
Current AIDA data file R35_22
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Attachment 1: bias1.png
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Attachment 2: bias2.png
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Attachment 3: temps.png
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Attachment 4: 1.png
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Attachment 5: 2.png
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Attachment 6: 3.png
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Attachment 7: 4.png
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Attachment 8: 5.png
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Attachment 9: 6.png
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Attachment 10: 7.png
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Attachment 11: 8.png
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Attachment 12: 9.png
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Attachment 13: 10.png
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Attachment 14: 11.png
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Attachment 15: 12.png
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Attachment 16: R34_25.txt
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*** TDR format 3.3.0 analyser - TD - October 2016
*** ERROR: READ I/O error: 5002
blocks: 32000
ADC data format: 229788876 ( 1082659.8 Hz)
Other data format: 31299124 ( 147467.1 Hz)
Sample trace data format: 0 ( 0.0 Hz)
Undefined format: 0 ( 0.0 Hz)
Other data format type: PAUSE: 78 ( 0.4 Hz)
RESUME: 78 ( 0.4 Hz)
SYNC100: 1941496 ( 9147.4 Hz)
FEE64 disc: 29351151 ( 138289.2 Hz)
MBS info: 6321 ( 29.8 Hz)
Other info: 0 ( 0.0 Hz)
ADC data range bit set: 4093 ( 19.3 Hz)
Timewarps: ADC: 0 ( 0.0 Hz)
PAUSE: 0 ( 0.0 Hz)
RESUME: 0 ( 0.0 Hz)
SYNC100: 0 ( 0.0 Hz)
FEE64 disc: 0 ( 0.0 Hz)
MBS info: 0 ( 0.0 Hz)
Undefined: 0 ( 0.0 Hz)
Sample trace: 0 ( 0.0 Hz)
*** Timestamp elapsed time: 212.245 s
FEE elapsed dead time(s) elapsed idle time(s)
1 0.179 0.189
2 0.433 0.089
3 0.000 0.000
4 0.000 0.000
5 0.000 0.000
6 0.013 0.000
7 0.000 0.000
8 0.000 0.000
9 0.013 0.000
10 0.000 0.000
11 0.000 0.000
12 0.000 0.000
13 0.007 0.000
14 0.062 0.000
15 0.000 0.000
16 0.000 0.000
17 1.155 1.085
18 0.973 1.009
19 0.663 0.668
20 0.044 0.000
21 0.006 0.000
22 0.036 0.000
23 0.144 0.000
24 0.000 0.000
25 0.000 0.000
26 0.000 0.000
27 0.000 0.000
28 0.000 0.000
29 0.000 0.000
30 0.000 0.000
31 0.000 0.000
32 0.000 0.000
*** Statistics
FEE ADC Data Other Data Sample Undefined Pause Resume SYNC100 Disc MBS Other HEC Data
0 0 0 0 0 0 0 0 0 0 0 0
1 10162396 10435966 0 0 4 4 80891 10355067 0 0 186
2 8634481 10195286 0 0 11 11 80791 10114473 0 0 12
3 6600962 88413 0 0 0 0 80948 7465 0 0 8
4 1958629 87328 0 0 0 0 80954 6374 0 0 47
5 9294993 90020 0 0 0 0 80958 9062 0 0 19
6 9092671 93303 0 0 2 2 80947 6031 6321 0 60
7 3892664 87399 0 0 0 0 80952 6447 0 0 75
8 3516156 88320 0 0 0 0 80956 7364 0 0 807
9 7290334 2388971 0 0 1 1 80955 2308014 0 0 40
10 6245189 317990 0 0 0 0 80955 237035 0 0 33
11 2282999 88753 0 0 0 0 80954 7799 0 0 46
12 3128778 87549 0 0 0 0 80957 6592 0 0 53
13 9271037 489645 0 0 2 2 80950 408691 0 0 88
14 8382022 3498809 0 0 4 4 80932 3417869 0 0 1213
15 8118269 89565 0 0 0 0 80958 8607 0 0 54
16 8635495 88556 0 0 0 0 80953 7603 0 0 43
17 25202848 1236221 0 0 17 17 80516 1155671 0 0 2
18 28365110 228865 0 0 14 14 80588 148249 0 0 40
19 22885157 94571 0 0 9 9 80696 13857 0 0 42
20 9479706 88801 0 0 3 3 80935 7860 0 0 668
21 7913982 108073 0 0 2 2 80953 27116 0 0 370
22 7542365 1148769 0 0 4 4 80941 1067820 0 0 150
23 16246723 88184 0 0 5 5 80901 7273 0 0 15
24 5645910 89767 0 0 0 0 80955 8812 0 0 22
25 0 0 0 0 0 0 0 0 0 0 0
26 0 0 0 0 0 0 0 0 0 0 0
27 0 0 0 0 0 0 0 0 0 0 0
28 0 0 0 0 0 0 0 0 0 0 0
29 0 0 0 0 0 0 0 0 0 0 0
30 0 0 0 0 0 0 0 0 0 0 0
31 0 0 0 0 0 0 0 0 0 0 0
32 0 0 0 0 0 0 0 0 0 0 0
*** Timewarps
FEE ADC Pause Resume SYNC100 Disc MBS Undefined Samples
0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0
2 0 0 0 0 0 0 0 0
3 0 0 0 0 0 0 0 0
4 0 0 0 0 0 0 0 0
5 0 0 0 0 0 0 0 0
6 0 0 0 0 0 0 0 0
7 0 0 0 0 0 0 0 0
8 0 0 0 0 0 0 0 0
9 0 0 0 0 0 0 0 0
10 0 0 0 0 0 0 0 0
11 0 0 0 0 0 0 0 0
12 0 0 0 0 0 0 0 0
13 0 0 0 0 0 0 0 0
14 0 0 0 0 0 0 0 0
15 0 0 0 0 0 0 0 0
16 0 0 0 0 0 0 0 0
17 0 0 0 0 0 0 0 0
18 0 0 0 0 0 0 0 0
19 0 0 0 0 0 0 0 0
20 0 0 0 0 0 0 0 0
21 0 0 0 0 0 0 0 0
22 0 0 0 0 0 0 0 0
23 0 0 0 0 0 0 0 0
24 0 0 0 0 0 0 0 0
25 0 0 0 0 0 0 0 0
26 0 0 0 0 0 0 0 0
27 0 0 0 0 0 0 0 0
28 0 0 0 0 0 0 0 0
29 0 0 0 0 0 0 0 0
30 0 0 0 0 0 0 0 0
31 0 0 0 0 0 0 0 0
32 0 0 0 0 0 0 0 0
*** Program elapsed time: 22.625s ( 1414.365 blocks/s, 88.398 Mb/s)
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Mon May 30 08:18:48 2016 |
CG, TD - PJCS reply | MACB settings |
Quote: |
14.00 MACB settings (from left -> right)
MACB# |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
Setting |
0 |
2 |
2 |
3 |
3 |
3 |
3 |
3 |
3 |
3 |
3 |
MACB#1 is grandparent in tree
#2 and #3 are parents
Rest are children.
14.05 MACBs 1 and 3 (master) replaced with spares. No change, clocks remain not locked.
PJCS _ reply The Master branch of the Tree needs to be set to 2 all the way to the Master.
So
GrandParent : 0
Parents : Master Branch 2 , Others 3
Children: Master Branch 2, Others 3.
Carry out a system Reset/Setup after changing to these settings.
Then System wide checks.
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