 Thu Nov 20 14:05:21 2014, Tom Davinson, AIDA Tests at STFC DL - PCS, TD 20x
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Configuration per Elog entries:
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Thu Sep 11 10:16:57 2014, Tom Davinson, AIDA Tests at STFC DL - PCS, SLT, TD 19x
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MSL type BB18-1000 2998-22 bias +200V I_L +3.27uA
BNC PB-5
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Thu Sep 11 16:12:06 2014, Tom Davinson and photos by Patrick, AIDA Tests at STFC DL - PCS, SLT, TD 19x
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Changes from configuration described by Elog entry https://elog.ph.ed.ac.uk/AIDA/3
are as follows:
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Wed Jan 28 16:12:52 2015, Tom Davinson, AIDA Tests at STFC DL - 27-28.1.15 - TD & PCS
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MSL type BB18-1000 2998-22 bias +200V I_L +3.52uA
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Tue May 3 15:45:17 2016, TD, AIDA Temperatures Log
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AIDA temperatures (ASIC, Virtex, PSU) are recorded in the file:
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Fri May 22 11:14:21 2015, TD, AIDA T9 test bed - nnaida11 DAQ stall
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AIDA T9 test bed
nnaida11 DAQ stall (0 AIDA SYNCs) at DAQ GO. Merger not in use. Fixed by STOP/GO cycle.
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Wed Nov 22 14:52:43 2023, NH, AIDA Pulser Calibration
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Connect pulser to all p+n FEEs
Turn on pulser, 100 Hz (attachment 3 for settings), rates OK (attachment 1)
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Wed Aug 9 14:40:28 2023, Carole, Nic, Jeroen, AIDA HV SUPPLY & PULSER TEST
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Tests with the HV supply (CAEN N1419ET) and Pulse Generator ( BNC PB-5 ) in the detector lab on the crate behind the DEGAS detectors, carried out the
9th August 2023
Both modules were plugged |
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Wed Aug 22 11:38:11 2018, OH, TD, AIDA GSI Setup Noise Tests 13x
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Currently seems to be a problem with the memory check in the system wide checks that produces the message shown
- attachment 1
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 Wed Aug 22 13:50:30 2018, OH, TD, Reply by PCS, AIDA GSI Setup Noise Tests
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> Currently seems to be a problem with the memory check in the system wide checks that produces the message shown
> - attachment 1
>
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Mon May 2 07:37:03 2016, TD, AIDA FEE layout
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UP
nnaida25
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Sun May 1 07:59:08 2016, CG,PV,TD, AIDA Detector Configuration
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UPSTREAM
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Sat May 9 11:28:32 2015, TD, AIDA DSSSD dis-assembly
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AIDA DSSSD #1-3 stack disassembled without problem. DSSSDs returned to boxes
in the BF3 AIDA storage area.
Attachments 1 & 2 show DSSSD #1 (3131-11)
- spot the difference! |
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Sat Oct 29 07:26:59 2016, TD, AIDA ADC & disc data synchronisation check 14x
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Following analysis of AIDA ADC & disc readout ( see https://elog.ph.ed.ac.uk/AIDA/404 )
changed timestamp resolution from 1us/channel to 20.48us/channel
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Fri Jun 10 12:51:19 2016, TD, ADC offsets - pass 1 -18.15 3 June 2016
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Column order:
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Sun May 28 09:55:11 2017, PV, ADC offset value from pulser walkthrough run May2017/R28 R29
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ADC offset calculation using data from pulser walkthrough runs, see:
https://elog.ph.ed.ac.uk/AIDA/603
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Tue Feb 9 11:44:21 2021, OH, TD, CA, LS, 9th Feb GSI Dry run 16x
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Database file - 2019Dec19-16.19.51
Current threshold at 0x64
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Thu Jun 8 23:57:26 2017, ZLiu, TD, 9June2017 8:00-16:00 32x
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08:06 System wide checks all ok
implantation profile - attachment 1
count rate - attachment 2
Bias and leakage currents
ok - attachment 3
DAQstatistics
08:30 BRIKEN and BigRIPS stop their DAQs
AIDA on file R7_604
08:32 BigRIPS starts run 3090
BRIKEN starts run 85
AIDA on file R7_604
08:44 BRIKEN and BigRIPS stop their DAQs |
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Wed Feb 10 10:56:02 2016, CG, TD, 9-10 February 2016 7x
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MSL type BB18(DS)-1000 serial 2998-22
Bias +200V, I_L +=6.540uA, ambient temperature +19.9 deg C
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Thu Nov 5 16:28:05 2015, CG, TD, 5 Nov 2015 - New kapton cable tests @ DL 11x
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New Kapton PCB design (2x 0.45m + inter-connecting PCB, no ground plane layers) under test with small system in T9.
3 cables modified to remove ground connection.
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