AIDA GELINA BRIKEN nToF CRIB ISOLDE CIRCE nTOFCapture DESPEC DTAS EDI_PSA 179Ta CARME StellarModelling DCF K40
  CARME, Page 15 of 34  ELOG logo
New entries since:Thu Jan 1 01:00:00 1970
ID Date Author Subject
  400   Sun May 14 11:55:12 2023 TDSunday 14 May
12.44 DSSSD#3 bias -149.95V leakage current -6.448uA temperature +19.7 deg C ( https://web-docs.gsi.de/~lestinsk/tempplot.php )

CRYRING cave lights ON - leakage current measurements @ 60s intervals

6.448
6.449
6.448
6.448
6.449
6.448
6.448
6.448
6.449
6.448

18.24 DSSSD#3 bias -149.95V leakage current -6.442uA temperature + 21.0 deg C ( https://web-docs.gsi.de/~lestinsk/tempplot.php )

CRYRING cave lights ON - leakage current measurements @ 60s intervals

6.441
6.441
6.441
6.441
6.441
6.442
6.442
6.442
6.440
6.441
  399   Sat May 13 11:34:25 2023 TD, RSSSaturday 13 May
12.34 DSSSD#3 bias -149.95V leakage current -6.763uA temperature +21.2 deg C ( https://web-docs.gsi.de/~lestinsk/tempplot.php )

CRYRING cave lights ON - leakage current measurements @ 60s intervals

6.763
6.764
6.764
6.765
6.767
6.767
6.767
6.767
6.768
6.769

12.48 CRYRING cave lights OFF

13.03 leakage current -6.771uA - no obvious change due to the CRYRING cave lighting

17.31 DSSSD#3 bias -149.95V leakage current -6.658uA temperature +21.0 deg C ( https://web-docs.gsi.de/~lestinsk/tempplot.php )

leakage current measurements @ 60s intervals

6.656
6.655
6.655
6.655
6.654
6.652
6.652
6.651
6.650
6.649

CRYRING cave temperature variations/cycles ~0.1 deg C at +21 deg C ambient temperature can produce leakage current variations ~60nA for a leakage current of ~6.6uA

td@winder:~/f77$ ./jgen
 *** Enter reference temperature (K)
294
 *** Enter minimum temperature, maximum temperature
 *** and temperature increment (K)
290 298 0.1

 Temperature (K)   Ratio (J(T)/J(294.0))

      290.0                0.702
      290.1                0.708
      290.2                0.714
      290.3                0.721
      290.4                0.727
      290.5                0.734
      290.6                0.740
      290.7                0.747
      290.8                0.754
      290.9                0.761
      291.0                0.767
      291.1                0.774
      291.2                0.781
      291.3                0.788
      291.4                0.795
      291.5                0.802
      291.6                0.809
      291.7                0.817
      291.8                0.824
      291.9                0.831
      292.0                0.839
      292.1                0.846
      292.2                0.854
      292.3                0.861
      292.4                0.869
      292.5                0.877
      292.6                0.884
      292.7                0.892
      292.8                0.900
      292.9                0.908
      293.0                0.916
      293.1                0.924
      293.2                0.932
      293.3                0.941
      293.4                0.949
      293.5                0.957
      293.6                0.966
      293.7                0.974
      293.8                0.983
      293.9                0.991
      294.0                1.000
      294.1                1.009
      294.2                1.018
      294.3                1.027
      294.4                1.036
      294.5                1.045
      294.6                1.054
      294.7                1.063
      294.8                1.072
      294.9                1.082
      295.0                1.091
      295.1                1.101
      295.2                1.110
      295.3                1.120
      295.4                1.130
      295.5                1.139
      295.6                1.149
      295.7                1.159
      295.8                1.169
      295.9                1.179
      296.0                1.190
      296.1                1.200
      296.2                1.210
      296.3                1.221
      296.4                1.231
      296.5                1.242
      296.6                1.253
      296.7                1.263
      296.8                1.274
      296.9                1.285
      297.0                1.296
      297.1                1.308
      297.2                1.319
      297.3                1.330
      297.4                1.342
      297.5                1.353
      297.6                1.365
      297.7                1.376
      297.8                1.388
      297.9                1.400

STOP *** Program ends
  398   Fri May 12 16:24:20 2023 RSS, TDV-I test

Since yesterday evening, the bottom right detector was at -150 V. In the morning, the current was quite stable ~ 6.77 uA. The bias was switched off, the foils opened, both of the detector arms were moved in and out three times, and the chamber was tightly covered again. A negative bias voltage was applied from 0 to 150 V in steps of 10 V one by one to all four detectors, and the V-I results can be seen in Attachments 1-4. All detectors seem to be fine. The variation of the current with time at a constant bias voltage of -150 V was checked for all detectors and the results are in Attachments 5-8. Also, with an applied bias voltage of -150 V to the bottom right and left detector, the detector arms were moved in and out three times which showed a variation of 1-2 nA and 1 nA in the leakage current. For further conditioning of the bottom right detector, it is again left with a negative bias voltage of 150 V over the weekend.

Attachment 1: detector_1.png
detector_1.png
Attachment 2: detector_2.png
detector_2.png
Attachment 3: detector_3.png
detector_3.png
Attachment 4: detector_4.png
detector_4.png
Attachment 5: detector_1_variation.png
detector_1_variation.png
Attachment 6: detector_2_variation.png
detector_2_variation.png
Attachment 7: detector_3_variation.png
detector_3_variation.png
Attachment 8: detector_4_variation.png
detector_4_variation.png
  397   Thu May 11 21:22:54 2023 RSS, TDV-I test

Today, the foil was opened, the pins on the bottom right detector were checked and looked fine, the right-hand arm was moved a bit in and then out, and the foil was tightly closed again. The negative bias voltage was applied from 0 to 50 V in steps of 10 V. During the measurement, the lights in the cave were switched off to ensure no leakage current from the light*. The results are shown in Attachment 1. To condition the detector, it was left at a negative bias voltage of 50 V for ~ 3 hours with lights on. No increase in current was seen (see Attachment 2), indicating the chamber was nicely covered with foil. Then the negative voltage was increased from 60 V to 150 V in steps of 10 V. No large current readings, like yesterday, were seen today (see Attachment 3). The detector was then left at -150 V for ~ 30 minutes with the current to be nearly stable with fluctuations in the range of 70-100 nA. The foil was then taken off to check if there are any dust particles on the detector surface. As can be seen in Attachment 6, some dust particle was found at the bias/multi-guard ring (MGR) boundary structures of the DSSSD. The area was then nicely cleaned with isopropanol + lab tissue wipe (see Attachment 7) and the chamber was covered with aluminum foil again. The negative bias voltage was applied from 0 to 150 V in steps of 10 V again and the results can be seen in attachment 5, indicating the response of the detector to be normal, unlike yesterday. Before calling the day off, the detector was left at -150 V overnight.

 

* Every time, before switching off the lights, it was checked that no one else was in the cave.

Attachment 1: test1.png
test1.png
Attachment 2: test2.png
test2.png
Attachment 3: test3.png
test3.png
Attachment 4: test4.png
test4.png
Attachment 5: test5.png
test5.png
Attachment 6: IMG_8800.jpg
IMG_8800.jpg
Attachment 7: IMG_8804.jpg
IMG_8804.jpg
  396   Wed May 10 19:06:18 2023 RSS, TDV-I test

To test the detectors, adaptors were installed on the feed through flanges. A negative bias voltage was applied in steps of 10 V from 0 to 150 V. The V-I plots are attached for the four detectors. Three detectors - top right, top left, and bottom left (in the direction of the beam) - are fine. For the bottom right detector (in the direction of the beam), the current was fluctuating and was considerably high (1st test). The adaptors connecting to this detector were removed and checked by applying the bias voltage which showed zero current for voltages ranging from 0 to - 150 V, confirming the adaptors to be fine. They were then exchanged by other adaptors and the V-I test was repeated again (2nd test) with fluctuating and high current values. One of the flanges connecting to this detector was found to be light-tight. These tests were done at an ambient temperature of 21 degrees. Also, we couldn't find the rest of the three SHV to 2x Lemo 00 cables for the detector HV.

Attachment 1: detector_1.png
detector_1.png
Attachment 2: detector_2.png
detector_2.png
Attachment 3: detector_3.png
detector_3.png
Attachment 4: detector_4.png
detector_4.png
  395   Tue May 2 15:02:09 2023 CB, JMAll detectors and harnesses mounted

Completed mounting harnesses and detectors.

The strain relief support for the bottom most two detectors on the feedthrough side was not mounted because we could not find enough MACOR parts and mounting flanges. We cannot find them in GSI, possibly they are somewhere not obvious in Edinburgh.

The strain relief on the detectors' side are still being manufactured.

 

We plan to test the detectors electrically from next week without moving the dolly. DR and OG to find a temporary mounting point for the manifold so that FEEs can be cooled in current configuration.

Attachment 1: 20230502_153410.jpg
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Attachment 2: 20230502_153503.jpg
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Attachment 3: 20230502_153509.jpg
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Attachment 4: 20230502_153511.jpg
20230502_153511.jpg
  394   Mon May 1 18:21:18 2023 CB, JMAll detectors mounted

Mounted four detectors on Carme ad well as four cable harnesses.

 

Cables for new, shorter harnesses appear still too long. Likely the model is not correct somehow.

 

One feedthrough flange was found to be damaged by an adaptor card. Tried to fix in vain. One pin is missing. Replaced with another.

Attachment 1: 20230501_191533.jpg
20230501_191533.jpg
Attachment 2: 20230501_191511.jpg
20230501_191511.jpg
Attachment 3: 20230501_145740.jpg
20230501_145740.jpg
  393   Mon May 1 08:26:09 2023 CB, JMLeft hand detectors remounted

(31 April)

Remounted 3335-12 on top and new 3335-1 on bottom of left hand plate. Used new dog legs and old standoffs.

 

Dismounted all harnesses and feedthroughs from CARME. Dismounted all blind flanges on right hand side. Also had to dismount bottom SAES feedthrough due to a bolt falling inside.

Remounted feedthough. Remounted left hand detector plate.

 

Prepared new 3335-11 and 3335-13 on top and bottom of right hand plate. Planning to mount tomorrow.

Also planning to start jacking in detectors to new harnesses.

 

Not possible to test any detector on the bench due to lack of appropriate multimeter probe. Will have to test with harnesses.

  392   Sun Apr 30 10:01:39 2023 CB, JMLeft hand detectors unmounted

(29 April)

Inspected CARME after opening. See attached. Some key takeaways.

- No visible damage to the detectors or the Kapton cables. No visible deposits or dust on the detectors either. 

- No damage even to the fragile thermocouple wires

- The strain relief on the top and bottom did nothing. Those on the sides may have helped.

- The split funnels on top fell and fortunately missed the detectors. We should not keep them. Unclear if they feel when moving CARME or during the beamtime but either is too dangerous. We need another solution or we'll have to do without.

- Obvious traces of white dust particles over the chamber. Most likely MACOR.

 

Jacked out harness for bottom left detector that was not accepting bias. MACOR shavings fell off while jacking out. MACOR connector on side with no pins is clearly damaged. See attached. Should not affect performance.

Tested bias pins - they work. No visible damage to the detector except one bias bond wire has disconnected. Possibly one more nearby. TD thinks this is not enough to explain observed behaviour.

 

Mounting a DSSD on the plate while it hangs in Carme appears possible but very risky. Dismounted whole left support plate, and right support plate. 

 

Unless a clear fault can be identified for either the bottom left detector or its harnesses, both the detector and the harnesses will be replaced. Plan to remount top left detector with the same harnesses.

Plan to mount two more detectors on the right hand plate.

Attachment 1: 20230428_181020.jpg
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Attachment 2: 20230428_181123.jpg
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Attachment 3: 20230428_181126.jpg
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Attachment 4: 20230428_181129.jpg
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Attachment 5: 20230428_181131.jpg
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Attachment 6: 20230428_181133.jpg
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Attachment 7: 20230428_181139.jpg
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Attachment 8: 20230428_181141.jpg
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Attachment 9: 20230429_150436.jpg
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Attachment 10: 20230429_150717.jpg
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Attachment 11: 20230429_151421.jpg
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Attachment 12: 20230429_151425.jpg
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Attachment 13: 20230429_151428.jpg
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Attachment 14: 20230429_151431.jpg
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Attachment 15: 20230429_151432.jpg
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Attachment 16: 20230429_151435.jpg
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Attachment 17: 20230429_151436.jpg
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Attachment 18: 20230429_151444.jpg
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Attachment 19: 20230429_151449.jpg
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Attachment 20: 20230429_151453.jpg
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Attachment 21: 20230429_152026.jpg
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Attachment 22: 20230429_152045.jpg
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Attachment 23: 20230429_160614.jpg
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Attachment 24: 20230429_162251.jpg
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Attachment 25: 20230429_162257.jpg
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Attachment 26: 20230429_172209.jpg
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  391   Sat Apr 29 10:12:58 2023 CB, JMCARME opened

(28 April)

Mounted rails on dolly. The rails don't smoothly connect to those on the Aluminium frame and some thin metal shims were required to get the correct height. A metal support had to be placed above the Delrin pads to support the rails above the gap between frames.

 

All side feet were mounted but extensive modifications were required to slotted feet due to them not being manufactured to drawing, and to Carme middle section flange width being incorrect (see previous entry).

 

Removed brakes and started sliding CARME out. The dolly and the aluminium frame came partly separated as the weight of the side feet was shifted on the latter. Strapped them together. No damage.

 

Kept sliding. Sliding when the carriages passed from one rail to the other was quite hard. The back carriage on the left looking downstream lost a single ball bearing when crossing over. A more sophisticated solution is probably required.

 

Once Carme was on the dolly, opened it using M8 jacking bolts and lifted away front and middle section. 

 

No obvious damage inside but strain relief did not work as intended. Photos to be uploaded after more detailed inspection on Saturday.

 

Plan to install right hand side detectors over the weekend. Unclear if bottom left detector is damaged and needs to be replaced.

Attachment 1: 20230428_094931.jpg
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Attachment 2: 20230428_155649.jpg
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Attachment 3: 20230428_164926.jpg
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Attachment 4: 20230428_155748.jpg
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Attachment 5: 20230428_165448.jpg
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Attachment 6: 20230428_174021.jpg
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Attachment 7: 20230428_181020.jpg
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Attachment 8: 20230428_181919.jpg
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  390   Thu Apr 27 19:43:23 2023 CB, JMPreparing to open

Removed turbo pump and set aside in a box. Considering switching to the other turbo to avoid degradation due to lack of use.

 

Installed bellows support and OG devised support to avoid bellows sagging when Carme is split open.

 

Attempted to install new CARME feet, but there were issues. Feet with slots produced do not match design drawings by PB. Slot is in the wrong side. Furthermore Carme interaction chamber flange thickness is 36 mm vs. 36.5 mm in drawing. DR can modify feet to make them fit tomorrow.

 

Now just waiting for rails to open CARME. Will arrive tomorrow or on Tuesday, after weekend and Mayday.

 

Attachment 1: 20230427_123456.jpg
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Attachment 2: 20230427_161602.jpg
20230427_161602.jpg
  389   Wed Apr 26 16:49:28 2023 CB, JMCARME dolly mostly built

Disconnected cables from CARME motors and turbo. The turbo has to go to allow Carme to slide out. Crane may be required to lift because it's in a very hard spot to access.

 

Dolly mostly built. See attached. Left side doesn't quite fit right by 1-2 mm. Might be okay anyway but will put some shims to avoid any shaking during sliding.

 

Waiting for the rails to arrive due to GSI procurement issues.

 

Plan to mount new feet and bellow support tomorrow.

Also plan to split CARME at the smaller flange towards the interaction chamber, after the bellows and before the bellows towards the magnet on the downstream side.

Attachment 1: 20230426_152121.jpg
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Attachment 2: 20230426_162619.jpg
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Attachment 3: 20230426_162627.jpg
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  388   Tue Apr 25 13:22:19 2023 JMCARME venting

CARME venting using nitrogen gas bottle. 

Coolant pipes dismounted from the chamber

Feed-through flange for n+n bias flange for bottom detector has a bent pin image attached. Clearer image of bent pin for ERNI connector used for aida03 also attached. All other feed-throughs and adaptor cards appear undamaged. 

Attachment 1: 20230425_134119.jpg
20230425_134119.jpg
Attachment 2: 20230425_132944.jpg
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  387   Mon Apr 24 21:24:26 2023 JMPreparation for CARME dismount

CARME currently in vacuum, pressure ~3E-10 mbar. Chamber to be vented tomorrow afternoon by vacuum division. We have active both pirani and hot cathode gauge to aid. 

Equipment removed from the chamber in preparation for dismount of CARME from the ring this week. Equipment removed includes:

  • Neg pump cabling
  • Heating wire
  • FEE electronic units and associated cabling (power, hdmi etc)
  • Stainless steel FEE holders
  • Red and blue cooling hoses

Attached image shows chamber following equipment removal. Adaptor cards still attached to feed-through flanges. ERNI connnectors examined, all fine except for FEE aida03 which has a bent pin (see attached image). Will dismount adaptor cards to examine further tomorrow. Feed-through flanges will also be examined to check for bent pins following adaptor card removal. 

New CARME frame is part constructed and is in the CRYRING area. Requires rails and castors which should arrive this week. The height of the frame will require shortening, to be level with the current frame. This will be looked into further tomorrow. 

Attachment 1: 20230424_155635.jpg
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Attachment 2: 20230424_155607.jpg
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Attachment 3: 20230424_150526.jpg
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  386   Wed Mar 22 16:33:32 2023 TDNIM WR source
Test of NIM WR source at Edinburgh

Attachment 1 - NIM WR source

NIM module upper SMA - DSO ch 1
NIM module lower SMA - DSO ch 2

Attachment 2

NO SYNC or CLK signals observed.

Noise observed with NIM bin power ON *and* OFF

Attachment 3

NIM WR source in EG&G Ortec NIM bin



... and with the Digilent Zybo board switched ON!


Attacments 4-7
Trigger ch 2
4, 40, 400 & 4000ns/div

Attachment 8
Trigger ch 1
4ns/div
Attachment 1: 20230322_155735.jpg
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Attachment 2: 20230322_160448.jpg
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Attachment 3: 20230322_160453.jpg
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Attachment 4: 20230322_181015.jpg
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Attachment 5: 20230322_181027.jpg
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Attachment 6: 20230322_181045.jpg
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Attachment 7: 20230322_181054.jpg
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Attachment 8: 20230322_180945.jpg
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  385   Wed Jan 18 13:32:36 2023 PJCSMACB settings with either Emulator or VETAR

When using the VITAR connected to the HDMI port of the root MACB the settings for all the MACB in the system 0x3.

This setting takes the Clock and Data line from the input HDMI and outputs it via teh HDMI output ports.

When using the Emulator connected via the SMA connectors on the back of the root MACB then the setting for the root MACB should be 0xD and all others should be 0x3.

Attached is the .jed file for programming the MACB and the .vhd source file to help with understanding of the settings.

Attachment 1: macb_apr20.jed
Attachment 2: macb_apr20.vhd
----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:03:27 03/16/2011 
-- Design Name: 
-- Module Name:    macb_top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
-- NOTE all in/out notations are relative to this unit
entity macb_apr20 is
    Port ( 
			  port1_sp : inout  STD_LOGIC_VECTOR (3 downto 0);
			  port2_sp : inout  STD_LOGIC_VECTOR (3 downto 0);
			  port3_sp : inout  STD_LOGIC_VECTOR (3 downto 0);
			  port4_sp : inout  STD_LOGIC_VECTOR (3 downto 0);
			  layer_sp : inout  STD_LOGIC_VECTOR (3 downto 0);
			  layer_trigger : out std_logic ;
           sync_return : in  STD_LOGIC_VECTOR (3 downto 1);
           selector : in  STD_LOGIC_VECTOR (3 downto 0);
           sync_select : out  STD_LOGIC_vector(1 downto 0 );
           clock200_select : out  STD_LOGIC_vector( 1 downto 0 ) ;
			  butis_divide_reset : out std_logic ;
			  butis_divide_s : out std_logic_vector( 2 downto 0 ) ;
			  clock_5 : in std_logic ;
			  sync_5 : in std_logic ;
			  trigger : in std_logic_vector( 3 downto 0 ) ;
           MBS_in : in  STD_LOGIC_VECTOR (3 downto 0);
           MBS_out : out  STD_LOGIC_VECTOR (3 downto 0));
end macb_apr20;

architecture Behavioral of macb_apr20 is
signal port1_spi :  STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port1_spo :  STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port1_t :  STD_LOGIC_VECTOR (3 downto 0) := ( others => '1' );
signal port2_spi :  STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port2_spo :  STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port2_t :  STD_LOGIC_VECTOR (3 downto 0) := ( others => '1' );
signal port3_spi :  STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port3_spo :  STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port3_t :  STD_LOGIC_VECTOR (3 downto 0) := ( others => '1' );
signal port4_spi :  STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port4_spo :  STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal port4_t :  STD_LOGIC_VECTOR (3 downto 0) := ( others => '1' );
signal layer_spi :  STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal layer_spo :  STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' );
signal layer_t :  STD_LOGIC_VECTOR (3 downto 0) := ( others => '1' );
signal seli : integer range 0 to 15 := 0  ;
-- well really
signal MBS_in_n : std_logic_vector( 3 downto 0 ) := "0000" ;
begin
MBS_in_n <= ( not MBS_in);
seli <= conv_integer(not selector) ;
-- MBS signal allocations to sp lines and HDMI pin. This maps to NIM connections
-- 0 :	MBS_clock10 	SP0	13
-- 1 :	MBS_reset		SP1	14
-- 2 :	MBS_reset_rq	SP2	15
-- 3 :	MBS_Trigger		SP3	16
layer_trigger <= trigger(0) or trigger(1) or trigger(2) or trigger(3) ;

-- divider controls set for pass-through
butis_divide_reset <= '1' ; -- for now don't reset ;

process ( seli , MBS_in_n, port1_spi, port2_spi, port3_spi, port4_spi, layer_spi, sync_return ,sync_5  )
-- note : & => concatenate
begin
	case seli is 
	when 0 => --- Master/ Root / MBS / Internal clock
		port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
		port1_t <= "0011" ; -- drive trigger and reset request only
		port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port2_t <= "0100" ; -- drive clock, reset, trigger only 
		port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port3_t <= "0100" ; -- drive clock, reset, trigger only
		port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port4_t <= "0100" ; -- drive clock, reset, trigger only
		layer_spo <= ( others => '0' ) ;
		layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
		sync_select <= "00" ; -- select sync from port 1 
		clock200_select <= "00" ; -- select internal 200 MHz oscillator
		MBS_out <=  MBS_in_n(3) & MBS_in_n(2) & port1_spi(1) & port1_spi(0) ;
		butis_divide_s <= "000" ; -- s2 is 0 for pass,
		
	when 1 => --- Master/ Root / MBS / BuTiS clock and SYNC
		port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
		port1_t <= "0011" ; -- drive trigger and reset request only
		port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port2_t <= "0100" ; -- drive clock, reset, trigger only 
		port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port3_t <= "0100" ; -- drive clock, reset, trigger only
		port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port4_t <= "0100" ; -- drive clock, reset, trigger only
		layer_spo <= ( others => '0' ) ;
		layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
		sync_select <= "01" ; -- select sync from external using SMA input 
		clock200_select <= "01" ; -- select external 200 MHz oscillator using SMA input
		MBS_out <=  MBS_in_n(3) & MBS_in_n(2) & port1_spi(1) & port1_spi(0) ;
		butis_divide_s <= "000" ; -- s2 is 0 for pass,

	when 2 => --- Master/ Branch / MBS / Next layer clock next layer SYNC
		port1_spo <= layer_spi(3) & layer_spi(2) & '0' & '0' ;
		port1_t <= "0011" ; -- drive trigger and reset request only
		port2_spo <= layer_spi(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port2_t <= "0100" ; -- drive clock, reset, trigger only 
		port3_spo <= layer_spi(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port3_t <= "0100" ; -- drive clock, reset, trigger only
		port4_spo <= layer_spi(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port4_t <= "0100" ; -- drive clock, reset, trigger only
		layer_spo <=  '0' & '0' & port1_spi(1) & port1_spi(0) ; -- drive the clock and reset down a layer
		layer_t <= "1100" ; -- just drive the bottom two bits to the "next" port
		sync_select <= "10" ; -- select sync from next_layer 
		clock200_select <= "10" ; -- select clock from next layer
		MBS_out <=  layer_spi(3) & layer_spi(2) & port1_spi(1) & port1_spi(0) ;
		butis_divide_s <= "000" ; -- s2 is 0 for pass,

	when 3 => --- Slave / Branch / MBS / Next layer clock and sync
		port1_spo <= layer_spi(3) & '0'  & layer_spi(1) & layer_spi(0);
		port1_t <= "0100" ; -- drive clock, reset, trigger only 
		port2_spo <= layer_spi(3) & '0' & layer_spi(1) & layer_spi(0) ;
		port2_t <= "0100" ; -- drive clock, reset, trigger only 
		port3_spo <= layer_spi(3) & '0' & layer_spi(1) & layer_spi(0) ;
		port3_t <= "0100" ; -- drive clock, reset, trigger only
		port4_spo <= layer_spi(3) & '0' & layer_spi(1) & layer_spi(0) ;
		port4_t <= "0100" ; -- drive clock, reset, trigger only
		layer_spo <=  '0' & '0' & '0' & '0' ; -- drive nothing
		layer_t <= "1111" ; -- just drive nothing down
		sync_select <= "10" ; -- select sync from next layer 
		clock200_select <= "10" ; -- select clock from next layer
		MBS_out <=  layer_spi ; -- map all the signals for monitoring ?
		butis_divide_s <= "000" ; -- s2 is 0 for pass,
		
	when 4 => --- Master/ Root / MBS / BuTiS clock / Internal SYNC / External timestamp reset
		port1_spo <= MBS_in_n(3) & '0' & MBS_in_n(1)  & '0' ;
		port1_t <= "0100" ; -- drive clock, reset, trigger only
		port2_spo <= MBS_in_n(3) & '0' & MBS_in_n(1)  & '0' ;
		port2_t <= "0100" ; -- drive clock, reset, trigger only 
		port3_spo <= MBS_in_n(3) & '0' & MBS_in_n(1)  & '0' ;
		port3_t <= "0100" ; -- drive clock, reset, trigger only
		port4_spo <= MBS_in_n(3) & '0' & MBS_in_n(1)  & '0' ;
		port4_t <= "0100" ; -- drive clock, reset, trigger only
		layer_spo <= ( others => '0' ) ;
		layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
		sync_select <= "00" ; -- select sync from port 1 
		clock200_select <= "01" ; -- select external 50 MHz oscillator using SMA input
		MBS_out <=  MBS_in_n(3) & MBS_in_n(2) & MBS_in_n(1) & sync_5 ;
		butis_divide_s <= "000" ; -- s2 is 0 for pass,

	when 5 => --- Master/ Root / MBS / External 50Mhz clock / Internal Sync
		port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
		port1_t <= "0011" ; -- drive trigger and reset request only
		port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port2_t <= "0100" ; -- drive clock, reset, trigger only 
		port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port3_t <= "0100" ; -- drive clock, reset, trigger only
		port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port4_t <= "0100" ; -- drive clock, reset, trigger only
		layer_spo <= ( others => '0' ) ;
		layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
		sync_select <= "00" ; -- select sync from port 1 
		clock200_select <= "01" ; -- select external SMA input 
		MBS_out <=  MBS_in_n(3) & MBS_in_n(2) & port1_spi(1) & port1_spi(0) ;
		butis_divide_s <= "000" ; -- s2 is 0 for pass through.
			
	when 6 => --- Master/ Root / MBS / External 100Mhz clock / Internal Sync
		port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
		port1_t <= "0011" ; -- drive trigger and reset request only
		port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port2_t <= "0100" ; -- drive clock, reset, trigger only 
		port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port3_t <= "0100" ; -- drive clock, reset, trigger only
		port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port4_t <= "0100" ; -- drive clock, reset, trigger only
		layer_spo <= ( others => '0' ) ;
		layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
		sync_select <= "00" ; -- select sync from port 1 
		clock200_select <= "01" ; -- select external SMA input 
		MBS_out <=  MBS_in_n(3) & MBS_in_n(2) & port1_spi(1) & port1_spi(0) ;
		butis_divide_s <= "100" ; -- s2 is 1 for external, 00 for /2.
		
	when 7 => --- Fast NIM input for each FEE / Next layer clock next layer SYNC
		port1_spo <= MBS_in_n(0) & layer_spi(2) & '0' & '0' ;
		port1_t <= "0011" ; -- drive trigger and reset request only
		port2_spo <= MBS_in_n(1) & '0' & port1_spi(1) & port1_spi(0) ;
		port2_t <= "0100" ; -- drive clock, reset, trigger only 
		port3_spo <= MBS_in_n(2) & '0' & port1_spi(1) & port1_spi(0) ;
		port3_t <= "0100" ; -- drive clock, reset, trigger only
		port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port4_t <= "0100" ; -- drive clock, reset, trigger only
		layer_spo <=  '0' & '0' & port1_spi(1) & port1_spi(0) ; -- drive the clock and reset down a layer
		layer_t <= "1100" ; -- just drive the bottom two bits to the "next" port
		sync_select <= "10" ; -- select sync from next_layer 
		clock200_select <= "10" ; -- select clock from next layer
		MBS_out <=  layer_spi(3) & layer_spi(2) & port1_spi(1) & port1_spi(0) ;
		butis_divide_s <= "000" ; -- s2 is 0 for pass,

	when 8 => --- Fast NIM input from Input 3 for each FEE / Next layer clock next layer SYNC
		port1_spo <= MBS_in_n(3) & layer_spi(2) & '0' & '0' ;
		port1_t <= "0011" ; -- drive trigger and reset request only
		port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port2_t <= "0100" ; -- drive clock, reset, trigger only 
		port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port3_t <= "0100" ; -- drive clock, reset, trigger only
		port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port4_t <= "0100" ; -- drive clock, reset, trigger only
		layer_spo <=  '0' & '0' & port1_spi(1) & port1_spi(0) ; -- drive the clock and reset down a layer
		layer_t <= "1100" ; -- just drive the bottom two bits to the "next" port
		sync_select <= "10" ; -- select sync from next_layer 
		clock200_select <= "10" ; -- select clock from next layer
		MBS_out <=  layer_spi(3) & layer_spi(2) & port1_spi(1) & port1_spi(0) ;
		butis_divide_s <= "000" ; -- s2 is 0 for pass,
	
	when 9 => --- Master/ Root / Internal clock / sync_returns to NIM
		port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
		port1_t <= "0011" ; -- drive trigger and reset request only
		port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port2_t <= "0100" ; -- drive clock, reset, trigger only 
		port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port3_t <= "0100" ; -- drive clock, reset, trigger only
		port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port4_t <= "0100" ; -- drive clock, reset, trigger only
		layer_spo <= ( others => '0' ) ;
		layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
		sync_select <= "00" ; -- select sync from port 1 
		clock200_select <= "00" ; -- select internal 200 MHz oscillator
		MBS_out <=  sync_return(3) & sync_return(2) & sync_return(1) & '0' ;
		butis_divide_s <= "000" ; -- s2 is 0 for pass,

	when 10 => --- Master/ Root / MBS / BuTiS clock /2 and SYNC
		port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
		port1_t <= "0011" ; -- drive trigger and reset request only
		port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port2_t <= "0100" ; -- drive clock, reset, trigger only 
		port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port3_t <= "0100" ; -- drive clock, reset, trigger only
		port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port4_t <= "0100" ; -- drive clock, reset, trigger only
		layer_spo <= "0000" ;
		layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
		sync_select <= "01" ; -- select sync from external using SMA input 
		clock200_select <= "01" ; -- select external 200 MHz oscillator using SMA input
		MBS_out <=  MBS_in_n ; -- for testing NIM I/O
		butis_divide_s <= "100" ; --  s2 = 1 and s1,s0 decode to 00=>/2 , 01=>/4, /8 , /16

	when 12 => --- Master/ Root / MBS / BuTiS clock /2 and SYNC
		port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
		port1_t <= "0011" ; -- drive trigger and reset request only
		port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port2_t <= "0100" ; -- drive clock, reset, trigger only 
		port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port3_t <= "0100" ; -- drive clock, reset, trigger only
		port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port4_t <= "0100" ; -- drive clock, reset, trigger only
		layer_spo <= ( others => '0' ) ;
		layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
		sync_select <= "01" ; -- select sync from external using SMA input 
		clock200_select <= "01" ; -- select external 200 MHz oscillator using SMA input
		MBS_out <=  MBS_in_n(3) & MBS_in_n(2) & port1_spi(1) & port1_spi(0) ;
		butis_divide_s <= "100" ; --  s2 = 1 and s1,s0 decode to 00=>/2 , 01=>/4, /8 , /16

	when 13 => --- Master/ Root / MBS / BuTiS clock /4 and SYNC
		port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
		port1_t <= "0011" ; -- drive trigger and reset request only
		port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port2_t <= "0100" ; -- drive clock, reset, trigger only 
		port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port3_t <= "0100" ; -- drive clock, reset, trigger only
		port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port4_t <= "0100" ; -- drive clock, reset, trigger only
		layer_spo <= ( others => '0' ) ;
		layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port
		sync_select <= "01" ; -- select sync from external using SMA input 
		clock200_select <= "01" ; -- select external 200 MHz oscillator using SMA input
		MBS_out <=  MBS_in_n(3) & MBS_in_n(2) & port1_spi(1) & port1_spi(0) ;
		butis_divide_s <= "101" ; --  s2 = 1 and s1,s0 decode to  01=>/4
		
	when 14 => --- Master/ Root / MBS / BuTiS clock /8 and SYNC
		port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ;
		port1_t <= "0011" ; -- drive trigger and reset request only
		port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
		port2_t <= "0100" ; -- drive clock, reset, trigger only 
		port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ;
... 161 more lines ...
Attachment 3: zybo.jpg
zybo.jpg
Attachment 4: MACB.jpg
MACB.jpg
  384   Thu Dec 8 14:41:19 2022 PJCSResults of tests on AIDA PSU in DL T9

We opened one up and soldered a co-ax cable to one of the +6v power contacts at the output of the filter board.

Connecting this to a 'scope we observed a level of +/- 5mv noise with no FEE connected.

Connecting one FEE made little difference.

Re-connected the FEE to the power supply in the cabinet and wired a co-ax to a spare FEE power plug. 

 

Ran the system with two FEEs on the bench top and two in the cabinet. The benchtop FEEs were connected to the NIM bin in the cabinet with copper braid.

Using a PB4 in the NIM bin and my test input cards on the FEE mezzanine connector, the following readings were taken using the 'integrate' function in the spectrum browser.

Shaping 8us, negative pulse.

aida02, ASIC1, ch0 Peak width => 16.58 channels ( full 16 bit spectra )

aida03, ASIC1, ch0 Peak width => 18.48 channels ( full 16 bit spectra )

aida04, ASIC1, ch0 Peak width => 18.05 channels ( full 16 bit spectra )

These could be better but the output of the PB4 was not perfect. I think ASIC 1 Ch0 is normally the worst on the mezzanine.

Attachments 1 to 6 are the waveforms and some zoomed in.

The co-ax from the power supply was connected to a 'scope and showed a noise level of +/-50mv. 

Fourier analysis of this noise showed two peaks 109kHz and 218kHz. ( Attachments 7 & 8 )

Attachment 1: IMG_5492.jpeg
IMG_5492.jpeg
Attachment 2: IMG_5493.jpeg
IMG_5493.jpeg
Attachment 3: IMG_5495_small.jpg
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Attachment 4: IMG_5496_small.jpg
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Attachment 5: IMG_5497_small.jpg
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Attachment 6: IMG_5498_small.jpg
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Attachment 7: IMG_5499_small.jpg
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Attachment 8: IMG_5500_small.jpg
IMG_5500_small.jpg
  383   Thu Dec 1 08:56:59 2022 AR TDThursday 1 December

Photos of noise observed at each of the AIDA PSU outputs by digital oscillscope.

DAQ GOing with waveforms enabled.

Connection from AIDA PSU to scope by DMM test probes, twisted cabling, 3mm jack plug/BNC adaptor.

Attachment 1,2,3 =  +5V

Attatchment 4 = -6V

Attatchment 5 = +7V

Attatchment 6 shows test setup

 

Repeat above test with *all* cables from AIDA PSU to FEE64s disconnected, i.e. no AIDA PSU load.

Attachment 7,8,9 =  +5V

Attatchment 10 = -6V

Attatchment 11 = +7V

Attachment 1: IMG_8378.JPG
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Attachment 2: IMG_8380.JPG
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Attachment 3: IMG_8382.JPG
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Attachment 4: IMG_8384.JPG
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Attachment 5: IMG_8385.JPG
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Attachment 6: IMG_8387.JPG
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Attachment 7: IMG_8393.JPG
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Attachment 8: IMG_8392.JPG
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Attachment 9: IMG_8391.JPG
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Attachment 10: IMG_8390.JPG
IMG_8390.JPG
Attachment 11: IMG_8389.JPG
IMG_8389.JPG
  382   Wed Nov 30 08:52:59 2022 AR TDWednesday 30 November

9:40

DSSD bias and leakage current values:

-99.99 V

-13.0960 uA

Pulsar peak widths (ch FWHM)

aida01 ~ 97

aida02 ~ 103

aida03 ~ 134

aida04 ~ 131

aida05 ~ 22

Pretty similar to what was found yesterday

 

15.30

Per Elog 375

Measured FEE64 voltages are as follows

@ISOL 4 AIDA PSU   @FEE64 aida05      nominal

(top-botttom)               (right-left)

+6.05V                        +5.26V                     +5V

+6.05V                        +5.26V                     +5V

+6.05V                        +5.26V                     +5V

-6.49V                         -6.26V                      -6V

+7.78V                        +7.46V                     +7V

 

Adjusted PowerStax PSU voltage pots of AIDA PSU ISOL 4

@ISOL 4 AIDA PSU   @FEE64 aida05      nominal

(top-botttom)               (right-left)

+5.79V                        +4.99V                     +5V

+5.79V                        +4.99V                     +5V

+5.79V                        +4.99V                     +5V

-6.23V                         -6.00V                      -6V

+7.32V                        +7.00V                     +7V

 

Attatchment 1-12 = BEFORE change

Attatchment 13+ = AFTER change

Pulsar peak widths (ch FWHM) AFTER CHANGE

aida01 ~ 100

aida02 ~ 96

aida03 ~ 130

aida04 ~ 130

aida05 ~ 22

Attachment 1: Screenshot_2022-11-30_at_10.11.36.png
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Attachment 2: Screenshot_2022-11-30_at_10.11.49.png
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Attachment 3: Screenshot_2022-11-30_at_10.12.21.png
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Attachment 4: Screenshot_2022-11-30_at_10.12.30.png
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Attachment 5: Screenshot_2022-11-30_at_10.12.36.png
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Attachment 6: Screenshot_2022-11-30_at_10.13.11.png
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Attachment 7: Screenshot_2022-11-30_at_10.13.18.png
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Attachment 8: Screenshot_2022-11-30_at_10.14.46.png
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Attachment 9: Screenshot_2022-11-30_at_10.15.14.png
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Attachment 10: Screenshot_2022-11-30_at_10.33.38.png
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Attachment 11: Screenshot_2022-11-30_at_10.34.34.png
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Attachment 12: Screenshot_2022-11-30_at_10.35.01.png
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Attachment 13: Screenshot_2022-11-30_at_15.13.50.png
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Attachment 14: Screenshot_2022-11-30_at_15.14.05.png
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Attachment 15: Screenshot_2022-11-30_at_15.14.35.png
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Attachment 16: Screenshot_2022-11-30_at_15.14.41.png
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Attachment 17: Screenshot_2022-11-30_at_15.14.48.png
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  381   Tue Nov 29 14:37:56 2022 AR TDTuesday 29 November

16:20

DSSD bias and leakage current values:

-99.99 V

-13.2535 uA

Pulsar peak widths (ch FWHM)

aida01 ~ 100

aida02 ~ 103

aida03 ~ 128

aida04 ~ 133

aida05 ~ 22

Pretty similar to what was found in august https://elog.ph.ed.ac.uk/CARME/377

 

 

 

 

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ELOG V3.1.4-unknown