 Wed Mar 20 17:02:53 2024, NH, /dev/sdd
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The following messages are in the system log very often:
Mar 20 18:00:56 aidas-gsi smartd[1076]: Device: /dev/sdd [SAT], 2224 Currently unreadable (pending) sectors
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Wed Mar 20 12:22:27 2024, NH, Wed Mar 20 9x
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Turn on AIDA for Dry Run demonstrations and so on
All system wide checks, temp, bias OK
Noise situation is dreadful (but has not been optimised). Deterioriation since first mounted, suspect cabling issues with bPlast and BB7. |
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Tue Mar 19 10:17:30 2024, NH, Dry Run 2024 - 19th March 24
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AIDA has 8 FEEs and 1 DSSSD
Aida08 (HDMI#12) had no WR again, I moved it to a different MACB and now it gets WR
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Mon Mar 18 18:04:43 2024, NH, Preparation for pre-s100 dry run (and test beam???)
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In preparation for the dry run the following *temporary* changes to the FEE numbering have been prepared
These should be reverted after the dry run to ensure cable->fee agreement again
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Fri Mar 15 16:29:57 2024, NH, Leakage currents
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The behaviour of the DSSSD leakage current at low voltages and during biases is unusual and varies depending on how the adapter boards are connected
To summarise the behaviour I have observed
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Thu Mar 14 13:00:23 2024, JB, NH, MA, AM, GA, Mounting and biasing DSSD 2
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new Downstream DSSD2: 3208-2/3208-5/3208-8
Covered with black cloth. |
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Thu Mar 14 12:13:17 2024, JB, NH, MA, Mounting and biasing DSSD 1
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Upstream bPlast mounted
new Upstream DSSD: 3208-2/3208-5/3208-8
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Wed Mar 13 13:02:19 2024, JB, NH, HA, MA, DSSD 1 biasing tests
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Dismounted Snout and biased DSSSD1 channels
leftmost waifer working
middle waifer reaches 90V then current ramps up |
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Tue Mar 12 16:16:49 2024, NH, TD, JB, HA, Summary of DSSSD Biasing 12.03
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DSSD#1 undergoes a breakdown at 90V, two of the three wafers show this
- The adapter PCBs themselves have no breakdown at 100V, indicating the issue is internal to the snout
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Mon Mar 11 15:19:44 2024, JB, NH, Priyanka, Michael Armstrong, Helena Albers, To Do: AIDA PCB tests
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To do:
1) Disconnect ribbon cables from p+n junction FEE64 adaptor PCBs of upstream DSSSD, apply c. 100V bias and check leakage current is zero
i.e. eliminate shorts in PCBs |
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Sun Mar 10 17:08:12 2024, NH, AIDA FEE Layout + Cabling Plan for S100
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Proposed FEE numbering and wiring plan for upcoming experiment S100 (2x Wide DSSSDs)
Image designed in draw.io, source attached
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Fri Mar 8 16:05:57 2024, JB, CC, TD, NH, Friday 8 March
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Bias tests of AIDA on individual wafers and in parallel. Spreadsheet can be found in attachment 1, and graphic results can be seen in Attachment 2. Summary:
Upstream detector cannot be biased in parallel nor individually. Downstream detector can be biased with positively and each wafer can individually be biased
negatively. In parallel, it was not possible to bias the downstream detector negatively as indicated by the tests below. |
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Thu Mar 7 15:15:29 2024, JB, NH, CC, AIDA HV Bias Test IV Curve
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AIDA I-V Test
Voltage (V)
Current
(uA)
10
1.43
20
2.065
30
2.415
40
2.64
50
2.825
60
2.99
70
3.185
80
3.58
90
5.01
100
9.4
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Voltage-Current test of newly installed AIDA snout. Breakdown observed at around ~92 V. Probably caused my light leakage into the snout, will investigate |
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Thu Mar 7 11:09:05 2024, HA, JB, CC, TD, MG, Thursday 7 March
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Snout assembly
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Tue Mar 5 09:10:01 2024, MA, JB, TD, Tuesday 5 March
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Old ribbon cable assemblies - attachments 1 2
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Mon Mar 4 11:35:30 2024, TD, Monday 4 March 11x
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12.30 FEE64 41:d7:cd ASIC mezzanine u/s, no data, ASIC temperature c. 20 deg C ( ambient ) low
Replaced ASIC mezzanine with new ASIC mezzanine
Installed as aida08
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Sun Mar 3 16:06:11 2024, TD, Sunday 3 March 24x
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17.00 FEE64 41:a0:71 ASIC #2 u/s
Replaced ASIC mezzanine with new ASIC mezzanine
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Mon Feb 26 13:17:51 2024, TD, Offline analysis of DEC23/R9_6 9x
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First pass analysis of data file /TapeData/DEC23/R9_6
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Wed Jan 31 15:27:07 2024, TD, Photos of water flow & dew point sensor interlock box
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Attachment 1 - 4 socket input connectors ( from sensor to interlock box )
Attachment 2 & 2 - 24V dc relays and internal wiring
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Mon Nov 13 11:46:54 2023, TD, Summary of AIDA 24cm x 8cm 'triple' DSSSD tests
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