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ID |
Date |
Author |
Subject |
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560
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Sun Apr 7 12:02:23 2024 |
TD | Sunday 7 April |
13.00 Cooling water temperature and flow OK - attachment 1
Test of AIDA 2x MSL type BB18(DS)-1000 24cm x 8cm DSSSDs 'as is' ( to be defined later in this Elog )
DSSSD bias & leakage current OK - attachment 2
Ambient temp 24.7 deg C, d.p. 7.1 deg C, RH 32.4%
Leakage current c. 6.6uA => 4nA/cm2/100um ( very good )
FEE64 temps OK - attachment 3
*except* aida02 ASIC temp which is known to be u/s
All system wide checks OK *except* aida02 and aida04 WR decoder status - attachment 4
WR timestamps OK - attachment 5
WR (info code 4 & 5), correlation scaler, PAUSE, RESUME, DISC, ADC data item stats - attachments 6-12
per FEE64 Rate spectra - attachments 13-15
per 1.8.W spectra - 20us FSR - attachments 16-1710129
14.45 FEE64 config check - per https://elog.ph.ed.ac.uk/DESPEC/562
FEE64 # PSU cable # MAC
1 1 ?
2 2 ?
3 3 ?
4 4 41 ee 71
5 5 ?
6 6 ?
7 7 f6 5a
8 8 41 d7 cd
9 ? ?
10 10 41 d0 0e
11 11 41 ee 0f
12 ? ?
13 13 ?
14 ? 0d 15
15 15 ?
16 16 f6 ed
? = no line of sight
- AIDA FEE64 PSU cabling - see attachment 18
Currently
PSU #1 1-3, 2-4, 9-5, 15-12
PSU #2 14-7, 6-8, 10-13, 11-16
Should be changed to
PSU #1 1-3, 2-4, 9-15, 5-12
PSU #2 14-7, 6-8, 10-11, 13-16
- AIDA snout mount to support frame - attachments 19 & 21
LHS ( looking downstream ) incorrect, RHS OK
- LKs
LK1 fitted aida02, aida04, aida06, aida08
LK3 fitted aida03, aida07, aida01, aida14
Significant gaps in snout ( i.e. possible light leaks ) where bPlas cabling exits snout - attachments 20 & 22
bPlas driver PCBs removed
bPlas ribbon cables, drain wires and Lemo 00.250 cabling disconnected - some cabling/drain wires touching snout etc
15.15 Adjust bPlas ribbon cables/drain wires/Lemo cables to ensure that none are touching snout or AIDA support frame - significant improvement
DSSSD bias & leakage current OK - attachment 23
FEE64 temps OK - attachment 24
ADC data item stats - attachments 25
per FEE64 Rate spectra - attachments 26
6x FEE64s < 20k. all FEE64s < 120k ( cf. 4x FEE64s < 20k, 5x FEE64s > 100k, 1x FEE64 320k earlier - attachment 12 )
per 1.8.W spectra - 20us FSR - attachments 27-28
17.15
LHS top hat washers
LK1, LK3
PSU power cables
tighten gnd screws
attachments 29-34
Note that some of the newly installed FEE64s have the incorrect rails fitted - FEE64s may ground to AIDA support stand
17.55 CAEN N1419ET LK removed -> floating outputs
18.15 +LK1 restored
attachments 35-40
18.40 +pwwer cycle
attachments 41-46 |
| Attachment 1: 20240407_125941.jpg
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| Attachment 2: Screenshot_from_2024-04-07_13-20-57.png
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| Attachment 3: Screenshot_from_2024-04-07_13-29-54.png
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| Attachment 4: Screenshot_from_2024-04-07_13-32-14.png
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| Attachment 5: Screenshot_from_2024-04-07_13-36-47.png
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| Attachment 6: Screenshot_from_2024-04-07_13-42-52.png
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| Attachment 7: Screenshot_from_2024-04-07_13-42-26.png
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| Attachment 8: Screenshot_from_2024-04-07_13-42-04.png
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| Attachment 9: Screenshot_from_2024-04-07_13-41-37.png
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| Attachment 10: Screenshot_from_2024-04-07_13-41-25.png
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| Attachment 11: Screenshot_from_2024-04-07_13-41-03.png
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| Attachment 12: Screenshot_from_2024-04-07_13-40-35.png
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| Attachment 13: Screenshot_from_2024-04-07_13-47-03.png
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| Attachment 14: Screenshot_from_2024-04-07_13-46-47.png
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| Attachment 15: Screenshot_from_2024-04-07_13-46-39.png
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| Attachment 16: Screenshot_from_2024-04-07_13-53-21.png
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| Attachment 17: Screenshot_from_2024-04-07_13-52-25.png
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| Attachment 19: 20240407_143510.jpg
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| Attachment 21: 20240407_143532.jpg
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| Attachment 22: 20240407_143539.jpg
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| Attachment 23: Screenshot_from_2024-04-07_15-10-39.png
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| Attachment 24: Screenshot_from_2024-04-07_15-10-53.png
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| Attachment 25: Screenshot_from_2024-04-07_15-13-00.png
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| Attachment 26: Screenshot_from_2024-04-07_15-12-49.png
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| Attachment 27: Screenshot_from_2024-04-07_15-11-54.png
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| Attachment 28: Screenshot_from_2024-04-07_15-11-06.png
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| Attachment 29: Screenshot_from_2024-04-07_17-14-23.png
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| Attachment 30: Screenshot_from_2024-04-07_17-13-49.png
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| Attachment 31: Screenshot_from_2024-04-07_17-11-59.png
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| Attachment 32: Screenshot_from_2024-04-07_17-11-47.png
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| Attachment 33: Screenshot_from_2024-04-07_17-11-38.png
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| Attachment 34: Screenshot_from_2024-04-07_17-11-19.png
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| Attachment 35: Screenshot_from_2024-04-07_18-12-38.png
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| Attachment 36: Screenshot_from_2024-04-07_18-12-53.png
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| Attachment 37: Screenshot_from_2024-04-07_18-13-03.png
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| Attachment 38: Screenshot_from_2024-04-07_18-14-51.png
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| Attachment 39: Screenshot_from_2024-04-07_18-14-12.png
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| Attachment 40: Screenshot_from_2024-04-07_18-13-10.png
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| Attachment 41: Screenshot_from_2024-04-07_18-44-32.png
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| Attachment 44: Screenshot_from_2024-04-07_18-43-21.png
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| Attachment 45: Screenshot_from_2024-04-07_18-43-12.png
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| Attachment 46: Screenshot_from_2024-04-07_18-42-56.png
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559
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Wed Apr 3 13:02:19 2024 |
NH | Merger for 16 FEEs |
Changed /MIDAS/Linux/startup/NewMerger
Change parameters -i and -l in master64 to 16 for 16 FEEs
Update NewMerger Options LinksAvailable to 16, LinksInUse to 1%1%1%1%1%1%1%1%1%1%1%1%1%1%1%1%
Fix NetVar RunOptions 1 (was 0)
Restart Merger HTTPd, Tape, Merger, MBS Spy
Reset/Setup/Go
16 Links green and status going, all good?
Bias DSSSDs and turn data transfer on
Merger connected, shows rate and updates... no rate in Tape Server?
.. Oops forget to turn on Output to data storage in merger!
Rate in tape server and to MBS: 7 MB/s
Merger, Tape and MBS working with 16 FEEs |
| Attachment 1: Screenshot_from_2024-04-03_14-15-02.png
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| Attachment 2: Screenshot_from_2024-04-03_14-15-25.png
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| Attachment 3: Screenshot_from_2024-04-03_14-15-36.png
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| Attachment 4: Screenshot_from_2024-04-03_14-15-45.png
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| Attachment 5: Screenshot_from_2024-04-03_14-15-52.png
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558
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Wed Apr 3 12:42:57 2024 |
NH | Report aida02 WR errors |
The WR error counter for aida02 seems to consantly rise
Tried reseating cable on both ends, no change
However clock status passed, aida02 has a correct WR timestamp and no FIFO/PLL errors seen
Edit to add: aida02 has the faulty ASIC temperature readout as well, related or coincidence? |
| Attachment 1: Screenshot_from_2024-04-03_13-43-48.png
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| Attachment 2: Screenshot_from_2024-04-03_13-43-38.png
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| Attachment 3: Screenshot_from_2024-04-03_13-43-58.png
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| Attachment 4: Screenshot_from_2024-04-03_13-44-14.png
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| Attachment 5: Screenshot_from_2024-04-03_13-44-36.png
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557
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Wed Apr 3 12:09:47 2024 |
NH | Report - aida06 frequently fails to boot first time (PHY error) |
When booting up AIDA aida06 usually crashes the first time, it fails to get IP from DHCP
After 180 seconds it reboots and seems to connect fine
Log file attached, key part (to me) is this:
27:03:24/14:13:19|Sending DHCP requests .
27:03:24/14:13:21|eth0: XLlTemac: PHY Link carrier lost.
27:03:24/14:13:21|..... timed out!
27:03:24/14:14:33|IP-Config: Reopening network devices...
27:03:24/14:14:33|eth0: XLlTemac: Options: 0x3fa
27:03:24/14:14:34|eth0: XLlTemac: allocating interrupt 19 for dma mode tx.
27:03:24/14:14:34|eth0: XLlTemac: allocating interrupt 18 for dma mode rx.
27:03:24/14:14:34|eth0: XLlTemac: speed set to 1000Mb/s
27:03:24/14:14:36|eth0: XLlTemac: Send Threshold = 24, Receive Threshold = 4
27:03:24/14:14:36|eth0: XLlTemac: Send Wait bound = 254, Receive Wait bound = 254
27:03:24/14:14:36|Sending DHCP requests ......
27:03:24/14:26:16| |
| Attachment 1: ttyUSB15
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27:03:24/14:12:59|
ISOL Version 1.00 Date 9th January 2017
27:03:24/14:12:59|
Flash base address=FC000000
27:03:24/14:12:59|
Set Flash to ASync Mode
27:03:24/14:12:59|
XST_SUCCESS
27:03:24/14:12:59|
Finished copying zImage to RAM
27:03:24/14:12:59|
27:03:24/14:12:59|
Found 0 errors checking kernel image
27:03:24/14:13:00|VHDL version number 0X03350706
27:03:24/14:13:00|
Based on AIDA Bootloader version number 1.2.0 -- 16th August 2012
27:03:24/14:13:00|
Starting LMK 3200 setup
27:03:24/14:13:00|
27:03:24/14:13:00|
Setting LMK03200 to standard clock settings -- External Clock 23Nov15
27:03:24/14:13:00|
.... SPI Base Address=0x81400000
27:03:24/14:13:00|
clk_control_reg=0x4
27:03:24/14:13:01|Next step is SPIconfig
27:03:24/14:13:01|
Control 32(0x81400000)=0x180
27:03:24/14:13:01|
SlaveSel(0x81400000)=0x3
27:03:24/14:13:01|
Ctrl(0x81400000)=0xE6
27:03:24/14:13:01|
Ctrl(0x81400000)=0x86
27:03:24/14:13:01|SPIconfig done now to set up the LMK3200 registers
27:03:24/14:13:01|LMK #0 : regInit[0]=0x80000000
27:03:24/14:13:01|LMK #0 : regInit[1]=0x10070600
27:03:24/14:13:01|LMK #0 : regInit[2]=0x60601
27:03:24/14:13:01|LMK #0 : regInit[3]=0x60602
27:03:24/14:13:01|LMK #0 : regInit[4]=0x60603
27:03:24/14:13:01|LMK #0 : regInit[5]=0x70624
27:03:24/14:13:01|LMK #0 : regInit[6]=0x70605
27:03:24/14:13:01|LMK #0 : regInit[7]=0x70606
27:03:24/14:13:01|LMK #0 : regInit[8]=0x70627
27:03:24/14:13:01|LMK #0 : regInit[9]=0x10000908
27:03:24/14:13:01|LMK #0 : regInit[10]=0xA0022A09
27:03:24/14:13:01|LMK #0 : regInit[11]=0x82800B
27:03:24/14:13:01|LMK #0 : regInit[12]=0x28C800D
27:03:24/14:13:01|LMK #0 : regInit[13]=0x830020E
27:03:24/14:13:01|LMK #0 : regInit[14]=0xC800180F
27:03:24/14:13:01|
Calibrate completed at 943 counts
27:03:24/14:13:01|
Setting Clock Control =0x0000000B, to set GOE and sync bit
27:03:24/14:13:01|
Ctrl @ SPIstop (0x81400000)=0x186
27:03:24/14:13:01|
Timeout waiting for Lock detect Stage 2 (Zero Delay), PWR_DWN=0x00000004
27:03:24/14:13:01|
27:03:24/14:13:01|
Finished Clock setup LMK03200
27:03:24/14:13:01|
completed LMK 3200 setup
27:03:24/14:13:02|
Loaded all four ASICs with default settings
27:03:24/14:13:02|
Setting the ADCs into calibration mode
27:03:24/14:13:02|
27:03:24/14:13:02|
Control 32(0x81400400)=0x180
27:03:24/14:13:02|
SlaveSel(0x81400400)=0xFF
27:03:24/14:13:02|
Ctrl(0x81400400)=0xE6
27:03:24/14:13:02|
Ctrl(0x81400400)=0x86
27:03:24/14:13:02|
Init : Config of AD9252 SPI ok
27:03:24/14:13:02|
27:03:24/14:13:02|
Ctrl @ SPIstop (0x81400400)=0x186ADCs initialised
27:03:24/14:13:02|
Cal not completed
27:03:24/14:13:02|
ADC calibrate failed
27:03:24/14:13:02|
Jumping to kernel simpleboot...
27:03:24/14:13:02|
27:03:24/14:13:02|
zImage starting: loaded at 0x00a00000 (sp: 0x00bc4eb0)
27:03:24/14:13:02|
Allocating 0x3b78cc bytes for kernel ...
27:03:24/14:13:02|
gunzipping (0x00000000 <- 0x00a0f000:0x00bc380e)...done 0x39604c bytes
27:03:24/14:13:05|
27:03:24/14:13:05|
Linux/PowerPC load: console=ttyS0 root=/dev/nfs ip=on rw mem=112M
27:03:24/14:13:12|
Finalizing device tree... flat tree at 0xbd1300
27:03:24/14:13:12|
Probing IIC bus for MAC... MAC address = 0xd8 0x80 0x39 0x41 0xee 0x71
27:03:24/14:13:12|Using Xilinx Virtex440 machine description
27:03:24/14:13:12|Linux version 2.6.31 (nf@nnlxb.dl.ac.uk) (gcc version 4.2.2) #34 PREEMPT Tue Nov 15 15:57:04 GMT 2011
27:03:24/14:13:12|Zone PFN ranges:
27:03:24/14:13:12| DMA 0x00000000 -> 0x00007000
27:03:24/14:13:12| Normal 0x00007000 -> 0x00007000
27:03:24/14:13:12|Movable zone start PFN for each node
27:03:24/14:13:13|early_node_map[1] active PFN ranges
27:03:24/14:13:13| 0: 0x00000000 -> 0x00007000
27:03:24/14:13:13|MMU: Allocated 1088 bytes of context maps for 255 contexts
27:03:24/14:13:13|Built 1 zonelists in Zone order, mobility grouping on. Total pages: 28448
27:03:24/14:13:13|Kernel command line: console=ttyS0 root=/dev/nfs ip=on rw mem=112M
27:03:24/14:13:13|PID hash table entries: 512 (order: 9, 2048 bytes)
27:03:24/14:13:13|Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
27:03:24/14:13:13|Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
27:03:24/14:13:13|Memory: 109680k/114688k available (3500k kernel code, 4852k reserved, 144k data, 130k bss, 168k init)
27:03:24/14:13:13|Kernel virtual memory layout:
27:03:24/14:13:13| * 0xffffe000..0xfffff000 : fixmap
27:03:24/14:13:13| * 0xfde00000..0xfe000000 : consistent mem
27:03:24/14:13:13| * 0xfde00000..0xfde00000 : early ioremap
27:03:24/14:13:13| * 0xd1000000..0xfde00000 : vmalloc & ioremap
27:03:24/14:13:13|NR_IRQS:512
27:03:24/14:13:13|clocksource: timebase mult[a00000] shift[22] registered
27:03:24/14:13:13|Console: colour dummy device 80x25
27:03:24/14:13:13|Mount-cache hash table entries: 512
27:03:24/14:13:13|NET: Registered protocol family 16
27:03:24/14:13:14|PCI: Probing PCI hardware
27:03:24/14:13:14|bio: create slab <bio-0> at 0
27:03:24/14:13:14|NET: Registered protocol family 2
27:03:24/14:13:14|IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
27:03:24/14:13:14|TCP established hash table entries: 4096 (order: 3, 32768 bytes)
27:03:24/14:13:14|TCP bind hash table entries: 4096 (order: 2, 16384 bytes)
27:03:24/14:13:14|TCP: Hash tables configured (established 4096 bind 4096)
27:03:24/14:13:14|TCP reno registered
27:03:24/14:13:14|NET: Registered protocol family 1
27:03:24/14:13:14|ROMFS MTD (C) 2007 Red Hat, Inc.
27:03:24/14:13:14|msgmni has been set to 214
27:03:24/14:13:14|io scheduler noop registered
27:03:24/14:13:14|io scheduler anticipatory registered
27:03:24/14:13:14|io scheduler deadline registered
27:03:24/14:13:14|io scheduler cfq registered (default)
27:03:24/14:13:14|Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
27:03:24/14:13:14|83e00000.serial: ttyS0 at MMIO 0x83e01003 (irq = 16) is a 16550
27:03:24/14:13:14|console [ttyS0] enabled
27:03:24/14:13:14|brd: module loaded
27:03:24/14:13:14|loop: module loaded
27:03:24/14:13:14|Device Tree Probing 'ethernet'
27:03:24/14:13:14|xilinx_lltemac 81c00000.ethernet: MAC address is now d8:80:39:41:ee:71
27:03:24/14:13:14|xilinx_lltemac 81c00000.ethernet: XLlTemac: using DMA mode.
27:03:24/14:13:15|XLlTemac: DCR address: 0x80
27:03:24/14:13:15|XLlTemac: buffer descriptor size: 32768 (0x8000)
27:03:24/14:13:15|XLlTemac: Allocating DMA descriptors with kmalloc
27:03:24/14:13:15|XLlTemac: (buffer_descriptor_init) phy: 0x6938000, virt: 0xc6938000, size: 0x8000
27:03:24/14:13:15|XTemac: PHY detected at address 7.
27:03:24/14:13:15|xilinx_lltemac 81c00000.ethernet: eth0: Xilinx TEMAC at 0x81C00000 mapped to 0xD1024000, irq=17
27:03:24/14:13:15|fc000000.flash: Found 1 x16 devices at 0x0 in 16-bit bank
27:03:24/14:13:15| Intel/Sharp Extended Query Table at 0x010A
27:03:24/14:13:15| Intel/Sharp Extended Query Table at 0x010A
27:03:24/14:13:15| Intel/Sharp Extended Query Table at 0x010A
27:03:24/14:13:15| Intel/Sharp Extended Query Table at 0x010A
27:03:24/14:13:15| Intel/Sharp Extended Query Table at 0x010A
27:03:24/14:13:15| Intel/Sharp Extended Query Table at 0x010A
27:03:24/14:13:15|Using buffer write method
27:03:24/14:13:15|cfi_cmdset_0001: Erase suspend on write enabled
27:03:24/14:13:15|cmdlinepart partition parsing not available
27:03:24/14:13:15|RedBoot partition parsing not available
27:03:24/14:13:15|Creating 5 MTD partitions on "fc000000.flash":
27:03:24/14:13:15|0x000000000000-0x000000500000 : "golden_firmware"
27:03:24/14:13:16|0x000000500000-0x000000800000 : "golden_kernel"
27:03:24/14:13:16|0x000000800000-0x000000d00000 : "user_firmware"
27:03:24/14:13:16|0x000000d00000-0x000000fe0000 : "user_kernel"
27:03:24/14:13:16|0x000000fe0000-0x000001000000 : "env_variables"
27:03:24/14:13:16|xilinx-xps-spi 81400400.hd-xps-spi: at 0x81400400 mapped to 0xD1028400, irq=20
27:03:24/14:13:16|SPI: XIlinx spi: bus number now 32766
27:03:24/14:13:16|xilinx-xps-spi 81400000.xps-spi: at 0x81400000 mapped to 0xD102C000, irq=21
27:03:24/14:13:16|SPI: XIlinx spi: bus number now 32765
27:03:24/14:13:16|mice: PS/2 mouse device common for all mice
27:03:24/14:13:16|Device Tree Probing 'i2c'
27:03:24/14:13:16| #0 at 0x81600000 mapped to 0xD1030000, irq=22
27:03:24/14:13:16|at24 0-0050: 1024 byte 24c08 EEPROM (writable)
27:03:24/14:13:16|TCP cubic registered
27:03:24/14:13:16|NET: Registered protocol family 17
27:03:24/14:13:16|RPC: Registered udp transport module.
27:03:24/14:13:16|RPC: Registered tcp transport module.
27:03:24/14:13:16|eth0: XLlTemac: Options: 0x3fa
27:03:24/14:13:17|eth0: XLlTemac: allocating interrupt 19 for dma mode tx.
27:03:24/14:13:17|eth0: XLlTemac: allocating interrupt 18 for dma mode rx.
27:03:24/14:13:17|eth0: XLlTemac: speed set to 1000Mb/s
27:03:24/14:13:19|eth0: XLlTemac: Send Threshold = 24, Receive Threshold = 4
27:03:24/14:13:19|eth0: XLlTemac: Send Wait bound = 254, Receive Wait bound = 254
27:03:24/14:13:19|Sending DHCP requests .
27:03:24/14:13:21|eth0: XLlTemac: PHY Link carrier lost.
27:03:24/14:13:21|..... timed out!
27:03:24/14:14:33|IP-Config: Reopening network devices...
27:03:24/14:14:33|eth0: XLlTemac: Options: 0x3fa
27:03:24/14:14:34|eth0: XLlTemac: allocating interrupt 19 for dma mode tx.
27:03:24/14:14:34|eth0: XLlTemac: allocating interrupt 18 for dma mode rx.
27:03:24/14:14:34|eth0: XLlTemac: speed set to 1000Mb/s
27:03:24/14:14:36|eth0: XLlTemac: Send Threshold = 24, Receive Threshold = 4
27:03:24/14:14:36|eth0: XLlTemac: Send Wait bound = 254, Receive Wait bound = 254
27:03:24/14:14:36|Sending DHCP requests ......
27:03:24/14:26:16|
ISOL Version 1.00 Date 9th January 2017
27:03:24/14:26:16|
Flash base address=FC000000
27:03:24/14:26:16|
Set Flash to ASync Mode
27:03:24/14:26:16|
XST_SUCCESS
27:03:24/14:26:16|
Finished copying zImage to RAM
27:03:24/14:26:17|
27:03:24/14:26:17|
Found 0 errors checking kernel image
27:03:24/14:26:18|VHDL version number 0X03350706
27:03:24/14:26:18|
Based on AIDA Bootloader version number 1.2.0 -- 16th August 2012
27:03:24/14:26:18|
Starting LMK 3200 setup
27:03:24/14:26:18|
27:03:24/14:26:18|
Setting LMK03200 to standard clock settings -- External Clock 23Nov15
27:03:24/14:26:18|
.... SPI Base Address=0x81400000
27:03:24/14:26:18|
clk_control_reg=0x4
27:03:24/14:26:18|Next step is SPIconfig
27:03:24/14:26:18|
Control 32(0x81400000)=0x180
27:03:24/14:26:18|
SlaveSel(0x81400000)=0x3
27:03:24/14:26:18|
Ctrl(0x81400000)=0xE6
27:03:24/14:26:18|
Ctrl(0x81400000)=0x86
27:03:24/14:26:18|SPIconfig done now to set up the LMK3200 registers
27:03:24/14:26:18|LMK #0 : regInit[0]=0x80000000
27:03:24/14:26:18|LMK #0 : regInit[1]=0x10070600
27:03:24/14:26:18|LMK #0 : regInit[2]=0x60601
27:03:24/14:26:19|LMK #0 : regInit[3]=0x60602
27:03:24/14:26:19|LMK #0 : regInit[4]=0x60603
27:03:24/14:26:19|LMK #0 : regInit[5]=0x70624
27:03:24/14:26:19|LMK #0 : regInit[6]=0x70605
27:03:24/14:26:19|LMK #0 : regInit[7]=0x70606
27:03:24/14:26:19|LMK #0 : regInit[8]=0x70627
27:03:24/14:26:19|LMK #0 : regInit[9]=0x10000908
27:03:24/14:26:19|LMK #0 : regInit[10]=0xA0022A09
27:03:24/14:26:19|LMK #0 : regInit[11]=0x82800B
27:03:24/14:26:19|LMK #0 : regInit[12]=0x28C800D
27:03:24/14:26:19|LMK #0 : regInit[13]=0x830020E
27:03:24/14:26:19|LMK #0 : regInit[14]=0xC800180F
27:03:24/14:26:19|
Calibrate completed at 943 counts
27:03:24/14:26:19|
Setting Clock Control =0x0000000B, to set GOE and sync bit
27:03:24/14:26:19|
Ctrl @ SPIstop (0x81400000)=0x186
27:03:24/14:26:19|
Timeout waiting for Lock detect Stage 2 (Zero Delay), PWR_DWN=0x00000004
27:03:24/14:26:19|
27:03:24/14:26:19|
Finished Clock setup LMK03200
27:03:24/14:26:19|
completed LMK 3200 setup
27:03:24/14:26:19|
Loaded all four ASICs with default settings
27:03:24/14:26:19|
Setting the ADCs into calibration mode
27:03:24/14:26:19|
27:03:24/14:26:19|
Control 32(0x81400400)=0x180
27:03:24/14:26:19|
SlaveSel(0x81400400)=0xFF
27:03:24/14:26:19|
Ctrl(0x81400400)=0xE6
27:03:24/14:26:19|
Ctrl(0x81400400)=0x86
27:03:24/14:26:19|
Init : Config of AD9252 SPI ok
27:03:24/14:26:19|
27:03:24/14:26:19|
Ctrl @ SPIstop (0x81400400)=0x186ADCs initialised
27:03:24/14:26:20|
ADCs calibrated
27:03:24/14:26:20|
27:03:24/14:26:20|
Control 32(0x81400400)=0x186
27:03:24/14:26:20|
SlaveSel(0x81400400)=0xFF
27:03:24/14:26:20|
Ctrl(0x81400400)=0xE6
27:03:24/14:26:20|
Ctrl(0x81400400)=0x86Config of AD9252 SPI ok
27:03:24/14:26:20|
27:03:24/14:26:20|
Ctrl @ SPIstop (0x81400400)=0x186Jumping to kernel simpleboot...
27:03:24/14:26:20|
27:03:24/14:26:20|
zImage starting: loaded at 0x00a00000 (sp: 0x00bc4eb0)
27:03:24/14:26:20|
Allocating 0x3b78cc bytes for kernel ...
27:03:24/14:26:20|
gunzipping (0x00000000 <- 0x00a0f000:0x00bc380e)...done 0x39604c bytes
27:03:24/14:26:23|
27:03:24/14:26:23|
Linux/PowerPC load: console=ttyS0 root=/dev/nfs ip=on rw mem=112M
27:03:24/14:26:29|
Finalizing device tree... flat tree at 0xbd1300
27:03:24/14:26:29|
Probing IIC bus for MAC... MAC address = 0xd8 0x80 0x39 0x41 0xee 0x71
27:03:24/14:26:30|Using Xilinx Virtex440 machine description
27:03:24/14:26:30|Linux version 2.6.31 (nf@nnlxb.dl.ac.uk) (gcc version 4.2.2) #34 PREEMPT Tue Nov 15 15:57:04 GMT 2011
27:03:24/14:26:30|Zone PFN ranges:
27:03:24/14:26:30| DMA 0x00000000 -> 0x00007000
27:03:24/14:26:30| Normal 0x00007000 -> 0x00007000
27:03:24/14:26:30|Movable zone start PFN for each node
27:03:24/14:26:30|early_node_map[1] active PFN ranges
27:03:24/14:26:30| 0: 0x00000000 -> 0x00007000
27:03:24/14:26:30|MMU: Allocated 1088 bytes of context maps for 255 contexts
27:03:24/14:26:30|Built 1 zonelists in Zone order, mobility grouping on. Total pages: 28448
27:03:24/14:26:31|Kernel command line: console=ttyS0 root=/dev/nfs ip=on rw mem=112M
27:03:24/14:26:31|PID hash table entries: 512 (order: 9, 2048 bytes)
27:03:24/14:26:31|Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
27:03:24/14:26:31|Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
27:03:24/14:26:31|Memory: 109680k/114688k available (3500k kernel code, 4852k reserved, 144k data, 130k bss, 168k init)
27:03:24/14:26:31|Kernel virtual memory layout:
27:03:24/14:26:31| * 0xffffe000..0xfffff000 : fixmap
27:03:24/14:26:31| * 0xfde00000..0xfe000000 : consistent mem
27:03:24/14:26:31| * 0xfde00000..0xfde00000 : early ioremap
27:03:24/14:26:31| * 0xd1000000..0xfde00000 : vmalloc & ioremap
27:03:24/14:26:31|NR_IRQS:512
27:03:24/14:26:31|clocksource: timebase mult[a00000] shift[22] registered
27:03:24/14:26:31|Console: colour dummy device 80x25
27:03:24/14:26:31|Mount-cache hash table entries: 512
27:03:24/14:26:31|NET: Registered protocol family 16
27:03:24/14:26:31|PCI: Probing PCI hardware
27:03:24/14:26:31|bio: create slab <bio-0> at 0
27:03:24/14:26:31|NET: Registered protocol family 2
27:03:24/14:26:31|IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
27:03:24/14:26:31|TCP established hash table entries: 4096 (order: 3, 32768 bytes)
27:03:24/14:26:32|TCP bind hash table entries: 4096 (order: 2, 16384 bytes)
27:03:24/14:26:32|TCP: Hash tables configured (established 4096 bind 4096)
27:03:24/14:26:32|TCP reno registered
27:03:24/14:26:32|NET: Registered protocol family 1
27:03:24/14:26:32|ROMFS MTD (C) 2007 Red Hat, Inc.
27:03:24/14:26:32|msgmni has been set to 214
27:03:24/14:26:32|io scheduler noop registered
27:03:24/14:26:32|io scheduler anticipatory registered
27:03:24/14:26:32|io scheduler deadline registered
27:03:24/14:26:32|io scheduler cfq registered (default)
27:03:24/14:26:32|Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
27:03:24/14:26:32|83e00000.serial: ttyS0 at MMIO 0x83e01003 (irq = 16) is a 16550
27:03:24/14:26:32|console [ttyS0] enabled
27:03:24/14:26:32|brd: module loaded
27:03:24/14:26:32|loop: module loaded
27:03:24/14:26:32|Device Tree Probing 'ethernet'
27:03:24/14:26:32|xilinx_lltemac 81c00000.ethernet: MAC address is now d8:80:39:41:ee:71
27:03:24/14:26:32|xilinx_lltemac 81c00000.ethernet: XLlTemac: using DMA mode.
27:03:24/14:26:32|XLlTemac: DCR address: 0x80
27:03:24/14:26:32|XLlTemac: buffer descriptor size: 32768 (0x8000)
27:03:24/14:26:32|XLlTemac: Allocating DMA descriptors with kmalloc
27:03:24/14:26:32|XLlTemac: (buffer_descriptor_init) phy: 0x6938000, virt: 0xc6938000, size: 0x8000
27:03:24/14:26:33|XTemac: PHY detected at address 7.
27:03:24/14:26:33|xilinx_lltemac 81c00000.ethernet: eth0: Xilinx TEMAC at 0x81C00000 mapped to 0xD1024000, irq=17
27:03:24/14:26:33|fc000000.flash: Found 1 x16 devices at 0x0 in 16-bit bank
27:03:24/14:26:33| Intel/Sharp Extended Query Table at 0x010A
27:03:24/14:26:33| Intel/Sharp Extended Query Table at 0x010A
27:03:24/14:26:33| Intel/Sharp Extended Query Table at 0x010A
27:03:24/14:26:33| Intel/Sharp Extended Query Table at 0x010A
27:03:24/14:26:33| Intel/Sharp Extended Query Table at 0x010A
27:03:24/14:26:33| Intel/Sharp Extended Query Table at 0x010A
27:03:24/14:26:33|Using buffer write method
27:03:24/14:26:33|cfi_cmdset_0001: Erase suspend on write enabled
27:03:24/14:26:33|cmdlinepart partition parsing not available
27:03:24/14:26:33|RedBoot partition parsing not available
27:03:24/14:26:33|Creating 5 MTD partitions on "fc000000.flash":
27:03:24/14:26:33|0x000000000000-0x000000500000 : "golden_firmware"
27:03:24/14:26:33|0x000000500000-0x000000800000 : "golden_kernel"
... 1850 more lines ...
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Tue Apr 2 18:37:21 2024 |
TD | S505 ADC offsets |
S505 ADC offsets using pulser walkthrough data from data file R1
ch = channel + ( module * 64 ) + ( range * 2048 )
adc_data( ch ) = INT( RSHIFT( ABS( adc_data( ch ) - 32768 ), 3 ) - offset( ch ) + 0.5 ) |
| Attachment 1: S505_calibration_data.txt
|
$variables
offset( 0) = 28.32
offset( 1) = 17.71
offset( 2) = -9.75
offset( 3) = -5.24
offset( 4) = -10.84
offset( 5) = 0.13
offset( 6) = 28.59
offset( 7) = 28.54
offset( 8) = 0.83
offset( 9) = -12.15
offset( 10) = 29.36
offset( 11) = -50.47
offset( 12) = 10.03
offset( 13) = -26.90
offset( 14) = 12.49
offset( 15) = 10.57
offset( 16) = 9.29
offset( 17) = 1.09
offset( 18) = 21.86
offset( 19) = -0.32
offset( 20) = 22.59
offset( 21) = -9999.99
offset( 22) = -20.22
offset( 23) = 6.61
offset( 24) = -8.80
offset( 25) = -1.15
offset( 26) = 13.08
offset( 27) = -9.03
offset( 28) = -2.67
offset( 29) = -9.42
offset( 30) = 8.07
offset( 31) = 19.01
offset( 32) = 6.86
offset( 33) = 15.16
offset( 34) = -3.89
offset( 35) = -18.80
offset( 36) = 17.79
offset( 37) = 16.45
offset( 38) = -0.74
offset( 39) = 0.69
offset( 40) = -14.59
offset( 41) = -10.02
offset( 42) = 11.38
offset( 43) = -2.57
offset( 44) = 15.48
offset( 45) = 14.57
offset( 46) = 2.95
offset( 47) = 30.70
offset( 48) = -12.55
offset( 49) = -15.61
offset( 50) = -6.61
offset( 51) = -7.10
offset( 52) = -33.20
offset( 53) = 21.42
offset( 54) = -4.07
offset( 55) = -18.23
offset( 56) = 8.83
offset( 57) = -22.74
offset( 58) = 11.47
offset( 59) = 10.67
offset( 60) = -28.65
offset( 61) = 15.29
offset( 62) = 5.76
offset( 63) = -11.57
offset( 64) = 1.95
offset( 65) = -9999.99
offset( 66) = 22.52
offset( 67) = 42.10
offset( 68) = -0.20
offset( 69) = 9.78
offset( 70) = -11.48
offset( 71) = -0.03
offset( 72) = -12.50
offset( 73) = 25.08
offset( 74) = 12.77
offset( 75) = -2.76
offset( 76) = 7.90
offset( 77) = 9.85
offset( 78) = 5.20
offset( 79) = -13.91
offset( 80) = 18.82
offset( 81) = -8.25
offset( 82) = -8.40
offset( 83) = 13.67
offset( 84) = -10.37
offset( 85) = 28.32
offset( 86) = 11.42
offset( 87) = 2.74
offset( 88) = -24.88
offset( 89) = 11.28
offset( 90) = -26.69
offset( 91) = 0.91
offset( 92) = 8.04
offset( 93) = 7.64
offset( 94) = 10.10
offset( 95) = -20.71
offset( 96) = 6.72
offset( 97) = -12.63
offset( 98) = 10.27
offset( 99) = 16.05
offset( 100) = 8.96
offset( 101) = 33.57
offset( 102) = 28.81
offset( 103) = 23.49
offset( 104) = 7.96
offset( 105) = 6.07
offset( 106) = 21.57
offset( 107) = 13.06
offset( 108) = 0.82
offset( 109) = -3.55
offset( 110) = -5.21
offset( 111) = 11.48
offset( 112) = 16.21
offset( 113) = -0.10
offset( 114) = 3.87
offset( 115) = 19.76
offset( 116) = -9.11
offset( 117) = 24.64
offset( 118) = 1.82
offset( 119) = -9999.99
offset( 120) = 22.80
offset( 121) = -7.37
offset( 122) = -18.32
offset( 123) = -24.74
offset( 124) = -4.71
offset( 125) = 19.64
offset( 126) = 53.61
offset( 127) = 6.57
offset( 128) = 3.21
offset( 129) = 7.20
offset( 130) = 5.55
offset( 131) = -3.40
offset( 132) = -16.40
offset( 133) = -1.71
offset( 134) = -14.85
offset( 135) = -29.53
offset( 136) = 0.68
offset( 137) = -0.41
offset( 138) = 17.59
offset( 139) = -28.92
offset( 140) = -8.79
offset( 141) = 11.69
offset( 142) = -5.80
offset( 143) = -8.21
offset( 144) = 13.90
offset( 145) = 11.27
offset( 146) = -17.02
offset( 147) = -8.19
offset( 148) = 6.14
offset( 149) = -13.13
offset( 150) = 15.41
offset( 151) = 0.12
offset( 152) = -5.02
offset( 153) = 4.25
offset( 154) = 3.84
offset( 155) = 13.34
offset( 156) = 16.79
offset( 157) = -36.21
offset( 158) = -2.18
offset( 159) = 12.94
offset( 160) = 2.05
offset( 161) = -17.31
offset( 162) = 18.38
offset( 163) = -7.17
offset( 164) = 6.59
offset( 165) = -13.36
offset( 166) = -12.11
offset( 167) = -3.91
offset( 168) = 10.97
offset( 169) = -25.72
offset( 170) = -11.53
offset( 171) = 1.94
offset( 172) = -12.76
offset( 173) = 18.55
offset( 174) = 13.49
offset( 175) = -9.45
offset( 176) = -10.19
offset( 177) = 18.69
offset( 178) = 24.49
offset( 179) = 30.44
offset( 180) = 41.95
offset( 181) = 1.55
offset( 182) = 20.88
offset( 183) = 4.76
offset( 184) = 15.80
offset( 185) = 12.37
offset( 186) = -13.03
offset( 187) = 15.64
offset( 188) = -8.44
offset( 189) = -3.02
offset( 190) = 10.57
offset( 191) = 6.88
offset( 192) = -17.81
offset( 193) = -5.77
offset( 194) = -18.29
offset( 195) = 17.62
offset( 196) = -30.66
offset( 197) = -7.37
offset( 198) = 36.32
offset( 199) = 3.42
offset( 200) = -21.92
offset( 201) = 15.88
offset( 202) = -17.33
offset( 203) = -2.71
offset( 204) = -21.06
offset( 205) = -4.53
offset( 206) = -1.59
offset( 207) = -9.54
offset( 208) = -0.04
offset( 209) = 23.57
offset( 210) = 13.83
offset( 211) = -9.28
offset( 212) = 12.42
offset( 213) = 23.85
offset( 214) = 7.90
offset( 215) = -7.29
offset( 216) = 26.18
offset( 217) = 33.05
offset( 218) = 32.10
offset( 219) = -8.10
offset( 220) = 16.16
offset( 221) = 3.94
offset( 222) = -18.22
offset( 223) = -16.84
offset( 224) = 5.79
offset( 225) = 21.07
offset( 226) = 45.18
offset( 227) = -13.85
offset( 228) = 6.76
offset( 229) = 13.59
offset( 230) = 8.28
offset( 231) = -9.32
offset( 232) = 21.30
offset( 233) = 7.02
offset( 234) = 24.11
offset( 235) = 16.26
offset( 236) = 11.46
offset( 237) = 2.16
offset( 238) = 7.19
offset( 239) = 18.45
offset( 240) = 6.65
offset( 241) = 6.56
offset( 242) = -33.59
offset( 243) = 14.71
offset( 244) = 21.28
offset( 245) = -0.73
offset( 246) = -10.29
offset( 247) = 28.50
offset( 248) = -11.37
offset( 249) = -18.92
offset( 250) = 23.12
offset( 251) = 8.87
offset( 252) = 9.64
offset( 253) = 16.43
offset( 254) = -2.70
offset( 255) = 26.14
offset( 256) = -4.99
offset( 257) = -10.88
offset( 258) = 27.41
offset( 259) = -3.48
offset( 260) = -11.18
offset( 261) = 12.60
offset( 262) = 22.19
offset( 263) = -20.16
offset( 264) = 20.32
offset( 265) = 9.66
offset( 266) = 13.30
offset( 267) = -12.64
offset( 268) = 53.69
offset( 269) = 23.15
offset( 270) = 43.60
offset( 271) = 48.58
offset( 272) = -13.12
offset( 273) = -12.57
offset( 274) = 35.19
offset( 275) = 14.84
offset( 276) = 33.05
offset( 277) = 13.73
offset( 278) = 45.45
offset( 279) = 55.49
offset( 280) = 48.13
offset( 281) = 3.86
offset( 282) = 28.44
offset( 283) = 23.73
offset( 284) = 11.53
offset( 285) = -19.46
offset( 286) = 10.81
offset( 287) = 17.23
offset( 288) = -13.85
offset( 289) = 30.17
offset( 290) = 10.70
offset( 291) = 28.06
offset( 292) = -14.35
offset( 293) = 23.46
offset( 294) = 15.16
offset( 295) = -25.15
offset( 296) = -15.03
offset( 297) = -24.74
offset( 298) = -5.94
... 215 more lines ...
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555
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Tue Apr 2 12:36:25 2024 |
JB, CC, NH | Installing FEE64s of DSSSD2 cont. |
Some additional checks
- check 'top hat' electrical isolators are correctly installed at each of the 4x mounting points of the AIDA snout assembly
- check snout is electrically isolated with respect to AIDA support assembly/stand, bPlas PCBs/cabling/ground/drain wires and BB7
- check LK1 installed aida02 or aida04 *and* aida06 or aida08 ( I assume these are the n+n Ohmic FEE64s? )
- check LK3 installed bottom, middle p+n junction FEE64s ( i.e. LK3 installed on 2 of 16 FEE64 adaptor PCBs )
- check FEE64 power cables are paired correctly, e.g. aida02 & aida04, aida01 & aida03 etc. Remember that the numbering of the power cables at the FEE64 PSUs may no longer correspond to which FEE64 is actually connected to that cable
- check test and test - cable daisy chains are removed
- check ground cabling attachment to Lemo 00.250 connectors is tight - they have tendency to loosen with handling
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553
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Thu Mar 28 09:18:53 2024 |
TD | Installing FEE64s of DSSSD2 |
Some additional checks
- check 'top hat' electrical isolators are correctly installed at each of the 4x mounting points of the AIDA snout assembly
- check snout is electrically isolated with respect to AIDA support assembly/stand, bPlas PCBs/cabling/ground/drain wires and BB7
- check LK1 installed aida02 or aida04 *and* aida06 or aida08 ( I assume these are the n+n Ohmic FEE64s? )
- check LK3 installed bottom, middle p+n junction FEE64s ( i.e. LK3 installed on 2 of 16 FEE64 adaptor PCBs )
- check FEE64 power cables are paired correctly, e.g. aida02 & aida04, aida01 & aida03 etc. Remember that the numbering of the power cables at the FEE64 PSUs may no longer correspond to which FEE64 is actually connected to that cable
- check test and test - cable daisy chains are removed
- check ground cabling attachment to Lemo 00.250 connectors is tight - they have tendency to loosen with handling
| Quote: |
|
Mounted on frame:
DSSD 1 (Upstream) : 3208-2/3208-5/3208-8
DSSD 2 (Downstream): 3208-3/3208-21/3208-22
Current mapping has been redone for better management.
| AIDA - FEE Mapping |
| DSSSD 1 |
DSSSD2 |
| FEE |
MAC |
FEE |
MAC |
| aida01 |
41:ba:8a |
aida06 |
41:05:15 |
| aida02 |
41:f6:b7 |
aida07 |
41:f6:5a |
| aida03 |
41:d8:21 |
aida08 |
41:d7:cd |
| aida04 |
41:a0:71 |
aida10 |
41:d0:0E |
| aida05 |
41:cf:ac |
aida13 |
41:d8:2b |
| aida09 |
41:ee:10 |
aida14 |
42:0d:15 |
| aida15 |
41:b4:0c |
aida11 |
41:EE:0f |
| aida12 |
41:ba:89 |
aida16 |
41:f6:ed |
Going to try optimising noise now.
DHCP updated
new ASIC settings: 2024Mar27-11.25.32 - 16 FEEs (2,4,6,8 n+n, rest p+n)
New layouts: /home/npg/LayOut/GSI_Triple_S100
New layout.txt
Firmware of aida11 updated from 0xea40704 to 0x3350706
Temps GOOD fig 5
Rates fig 6, 7
Check adapter alignment aida14 and aida16
bPlas left/right cables are not insulated and shorting to the snout
Logs on nnpi1 archived and deleted, start again
All 16 FEEs are showing USB logging connectivity and can be monitored with Pi_Monitor
From waveforms aida08 and aida16 are quite unhappy. The rest don't seem too bad. DSSSD 1 is much quieter than it was before!
White Rabbit Analysis: aida02 has lots of WR error counter, HDMI reseat needed
aida09-12 have no WR timestamp, the cable to the MACB is bad or the MACB is bad.
Not needed to fix right now (for noise testing)
Turn off bPlas
We see the noise drop a lot
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552
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Wed Mar 27 14:22:35 2024 |
JB, NH | Installing FEE64s of DSSSD2 |
Mounted on frame:
DSSD 1 (Upstream) : 3208-2/3208-5/3208-8
DSSD 2 (Downstream): 3208-3/3208-21/3208-22
Current mapping has been redone for better management.
| AIDA - FEE Mapping |
| DSSSD 1 |
DSSSD2 |
| FEE |
MAC |
FEE |
MAC |
| aida01 |
41:ba:8a |
aida06 |
41:05:15 |
| aida02 |
41:f6:b7 |
aida07 |
41:f6:5a |
| aida03 |
41:d8:21 |
aida08 |
41:d7:cd |
| aida04 |
41:a0:71 |
aida10 |
41:d0:0E |
| aida05 |
41:cf:ac |
aida13 |
41:d8:2b |
| aida09 |
41:ee:10 |
aida14 |
42:0d:15 |
| aida15 |
41:b4:0c |
aida11 |
41:EE:0f |
| aida12 |
41:ba:89 |
aida16 |
41:f6:ed |
Going to try optimising noise now.
DHCP updated
new ASIC settings: 2024Mar27-11.25.32 - 16 FEEs (2,4,6,8 n+n, rest p+n)
New layouts: /home/npg/LayOut/GSI_Triple_S100
New layout.txt
Firmware of aida11 updated from 0xea40704 to 0x3350706
Temps GOOD fig 5
Rates fig 6, 7
Check adapter alignment aida14 and aida16
bPlas left/right cables are not insulated and shorting to the snout
Logs on nnpi1 archived and deleted, start again
All 16 FEEs are showing USB logging connectivity and can be monitored with Pi_Monitor
From waveforms aida08 and aida16 are quite unhappy. The rest don't seem too bad. DSSSD 1 is much quieter than it was before!
White Rabbit Analysis: aida02 has lots of WR error counter, HDMI reseat needed
aida09-12 have no WR timestamp, the cable to the MACB is bad or the MACB is bad.
Not needed to fix right now (for noise testing)
Turn off bPlas
We see the noise drop a lot |
| Attachment 1: Screenshot_2024-03-15_at_14-41-48_Spectrum_Browser_aidas-gsi.png
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| Attachment 2: Screenshot_2024-03-15_at_14-44-59_Statistics_aidas-gsi.png
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| Attachment 3: Screenshot_2024-03-15_at_14-55-07_System_wide_Checks_aidas-gsi.png
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| Attachment 4: Screenshot_2024-03-15_at_14-57-19_Temperature_and_status_scan_aidas-gsi.png
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| Attachment 5: Screenshot_from_2024-03-27_14-51-12.png
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| Attachment 6: Screenshot_from_2024-03-27_14-53-05.png
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| Attachment 7: Screenshot_from_2024-03-27_14-53-56.png
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| Attachment 8: Screenshot_from_2024-03-27_15-31-10.png
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| Attachment 9: Screenshot_from_2024-03-27_15-35-38.png
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| Attachment 10: Screenshot_from_2024-03-27_15-36-13.png
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| Attachment 11: Screenshot_from_2024-03-27_16-14-44.png
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| Attachment 12: Screenshot_from_2024-03-27_16-15-00.png
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| Attachment 13: Screenshot_from_2024-03-27_16-15-27.png
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| Attachment 14: Screenshot_from_2024-03-27_16-15-56.png
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551
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Tue Mar 26 18:56:03 2024 |
TD | USB-controlled ac mains relay interlock box - wiring |
Sensor ( 4 pins )
Red +24V
Blue 0V
Yellow } contact
Green } closure in ( short these two wires together for logic 1 )
N.B. yellow and green wires of unused inputs must be connected together
Output ( 3 pins ) to USB-controlled ac mains relay
Red NC ( normally closed - with respect to COM with no power applied, single pole double throw relay out )
Blue NO ( normally open - with respect to COM with no power applied, single pole double throw relay out )
Green COM |
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550
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Tue Mar 26 10:32:05 2024 |
NH, JB | Tue 26 March |
Taken 4 FEE64s from CRYRING (the 4 easiest to access)
41:d8:2b
41:f6:5a
41:ee:71
41:d0:0e
In addition a FEE without rails marked only 20 was found in my old office for 5
- This probably came in a shipment to/for repairs
DSSSD#1 unbiased
DESPEC Platform moved out of beam and gamma platform moved from AIDA
JB works on grounding the original 8 DSSSD#1 FEEs
Connected grounding from ribbon cable drain to adapter PCB
Ground loop connected
AIDA rates unchanged bad still fig 1
Waves fig 2 (p+n 6000-9000)
Waves fig 3 (n+n 8000-10000)
Statistics fig 4 |
| Attachment 1: Screenshot_from_2024-03-26_14-39-35.png
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| Attachment 2: Screenshot_from_2024-03-26_14-40-05.png
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| Attachment 3: Screenshot_from_2024-03-26_14-40-30.png
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| Attachment 5: 20240326_144539.jpg
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| Attachment 9: 20240326_144627.jpg
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549
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Fri Mar 22 08:31:39 2024 |
TD | Friday 22 March |
09.30 Systems check
CAEN N1419ET only channel #0 ON, all other channels off
DSSSD bias -120V leakage current -5.500uA - attachment 1
Leakage current of 5.5uA corresponds to c. 3nA/cm2/100um indicating high quality device ( assuming ambient temperature c. 21 deg C )
FEE64 temperatures OK *except* aida02 ASIC temperature - attachment 2
N.B. aida02 ASIC temperature sensor faulty - reading > 500 deg C - probably poor connection FEE64-ASIC mezzanine
All system wide checks OK *except*
aida04 WR decoder status 0x10 - attachment 3
WR timestamps OK - attachment 4
09.42 NH reports "195au implanting in aida, Ca 100 per spill"
ASIC settings
LEC/MEC slow comparator 0x64, LEC/MEC fast comparator 0xff, HEC comarator 0x2
aida02 and aida04 negative input polarity ( n+n Ohmic strips ), all other FEE64s positive input polarity
09.46 all histograms and stats zero'd
ADC, DISC, PAUSE, RESUME & Correlation Scaler data items stats - attachments 5-9
per FEE64 1.8.W spectra - 20us FSR - attachments 10-11
aida08 noise significantly lower than all other FEE64s
per FEE64 1.8.H spectra - attachments 12-13
data suggests 195Au ions are focussed on central Si wafer, ion energies to c. 5GeV, no evidence lower A/Z ( fission ) ions with lower energy loss
per FEE64 1.8.L spectra - attachments 14-15
per FEE64 Rate Stat spectra - attachments 16-19
Merger, TapeServer - attachments 20-21
Merger idle !?
Tape Server no storage mode but forwarding data at c. 1Mb/s
data file R31
13.30 NH reports "beam over"
DSSSD bias -120V leakage current -6.500uA - attachment 22
FEE64 temperatures OK *except* aida02 ASIC temperature - attachment 23
N.B. aida02 ASIC temperature sensor faulty - reading > 500 deg C - probably poor connection FEE64-ASIC mezzanine
All system wide checks OK *except*
aida05 & aida07 FPGA timestamp errors - attachment 24
aida04 WR decoder status 0x10 - attachment 25
WR timestamps OK - attachment 26
ADC data items stats - attachments 27
per FEE64 Rate spectra - attachments 28-29
per FEE64 1.8.L spectra - attachments 30-31
per FEE64 1.8.H spectra - attachments 32-33
per FEE64 1.8.W spectra - 20us FSR - attachments 34-35
Merger, TapeServer - attachments 36-37
Merger idle !?
Tape Server no storage mode but forwarding data at c. 1Mb/s
data file R31
20:30 AIDA Powered down
DSSSD remains biased at -120V, monitor the current over the weekend (Grafana)
Merger still showing idle... "no data to storage" makes xfer Links disappear?
Tape server stopped
11.20 Saturday 23 March
Grafana DSSSD bias/leakage current monitor screenshot - attachment 38
https://despec-vm-01.gsi.de/grafana/d/6SAfgl0Mz/aida?orgId=1&refresh=1m&from=now-2d&to=now
DSSSD#1 leakage current recovered to c. pre-beam values
08.05 Monday 25 March
Grafana DSSSD bias/leakage current monitor screenshot - attachment 39 |
| Attachment 1: Screenshot_from_2024-03-22_09-32-58.png
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| Attachment 2: Screenshot_from_2024-03-22_09-34-54.png
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| Attachment 3: Screenshot_from_2024-03-22_09-39-03.png
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| Attachment 17: Screenshot_from_2024-03-22_09-52-45.png
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| Attachment 18: Screenshot_from_2024-03-22_09-52-13.png
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| Attachment 19: Screenshot_from_2024-03-22_09-51-47.png
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| Attachment 20: Screenshot_from_2024-03-22_10-04-22.png
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| Attachment 21: Screenshot_from_2024-03-22_10-03-53.png
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| Attachment 28: Screenshot_from_2024-03-22_14-40-04.png
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| Attachment 29: Screenshot_from_2024-03-22_14-39-30.png
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| Attachment 32: Screenshot_from_2024-03-22_14-36-28.png
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| Attachment 37: Screenshot_from_2024-03-22_14-40-57.png
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| Attachment 38: Capture_2.PNG
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| Attachment 39: Capture_3.PNG
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547
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Fri Mar 22 08:29:55 2024 |
TD | Anydesk restarted remotely |
Anydesk restarted remotely per https://elog.ph.ed.ac.uk/CARME/489
Anydesk address now restored to 832827869 |
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546
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Fri Mar 22 08:22:43 2024 |
NH, AM, MP, CC | Thu Mar 21 |
> Fig 1-3: Noise situation at real thresholds (0xa p+n, 0xf n+n)
>
> Fig 4-6: After AM and MP turn off Mesytec Preamps
>
> No difference
I think there is a difference in the 1.8.W spectra - the 100kHz ripple is reduced significantly when the Mesytec preamps are switched off. |
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545
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Fri Mar 22 07:34:54 2024 |
NH, JB | Au Beam |
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544
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Thu Mar 21 15:41:49 2024 |
NH, AM, MP, CC | Thu Mar 21 |
Fig 1-3: Noise situation at real thresholds (0xa p+n, 0xf n+n)
Fig 4-6: After AM and MP turn off Mesytec Preamps
No difference |
| Attachment 1: Screenshot_from_2024-03-21_16-17-59.png
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| Attachment 2: Screenshot_from_2024-03-21_16-18-25.png
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| Attachment 4: Screenshot_from_2024-03-21_16-39-12.png
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543
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Wed Mar 20 17:02:53 2024 |
NH | /dev/sdd |
The following messages are in the system log very often:
Mar 20 18:00:56 aidas-gsi smartd[1076]: Device: /dev/sdd [SAT], 2224 Currently unreadable (pending) sectors
Mar 20 18:00:56 aidas-gsi smartd[1076]: Device: /dev/sdd [SAT], 257 Offline uncorrectable sectors
This (to me) suggests /dev/sdd may be failing. It should be backed up and later replaced (it is not used at the moment for /TapeData, older disk) |
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542
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Wed Mar 20 12:22:27 2024 |
NH | Wed Mar 20 |
Turn on AIDA for Dry Run demonstrations and so on
All system wide checks, temp, bias OK
Noise situation is dreadful (but has not been optimised). Deterioriation since first mounted, suspect cabling issues with bPlast and BB7.
Note thresholds at 0x32 (!!!) to not brutalise the DAQs during testing
aida08 seems OK
Server running to MBS totally fine
18:00
Carole grounded some of the Bplast and this reduced the rates in AIDA, although they are a bit fluctuatey. Due to position constraints she couldn't ground it all
Also AIDA ribbon cables are not grounded yet
The indication is these fixes should make a lot of difference to the situation
AIDA is now powered off for the end of day |
| Attachment 1: Screenshot_from_2024-03-20_13-20-43.png
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| Attachment 2: Screenshot_from_2024-03-20_13-20-54.png
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| Attachment 8: Screenshot_from_2024-03-20_13-25-02.png
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| Attachment 9: Screenshot_from_2024-03-20_13-25-13.png
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541
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Tue Mar 19 10:17:30 2024 |
NH | Dry Run 2024 - 19th March 24 |
AIDA has 8 FEEs and 1 DSSSD
Aida08 (HDMI#12) had no WR again, I moved it to a different MACB and now it gets WR
The MACB (currently with jsut HDMI#10) seems issues, check/replace the upstream HDMI and thent eh MACB (after dry run!)
DSSSD#1 biased to -120 V, leakage current 5.6 uA (fig 1)
(also on Grafana)
Temps OK fig2
System Checks (fig3-5)
Clocks OK
aida07 fails calibration, others OK
WR OK (aida04 0x10, seems OK)
FPGA OK
Did "Synchronise ASIC clocks" to align ASIC clocks
(Notes for scalers: SC41L HDMI 5, SCI41R HDMI 9)
18:12 FRS is taking beam, AIDA is powered off and unbiased |
| Attachment 1: Screenshot_from_2024-03-19_13-44-34.png
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| Attachment 2: Screenshot_from_2024-03-19_13-44-22.png
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| Attachment 3: Screenshot_from_2024-03-19_13-44-04.png
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| Attachment 4: Screenshot_from_2024-03-19_13-43-44.png
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| Attachment 5: Screenshot_from_2024-03-19_13-43-24.png
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540
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Mon Mar 18 18:04:43 2024 |
NH | Preparation for pre-s100 dry run (and test beam???) |
In preparation for the dry run the following *temporary* changes to the FEE numbering have been prepared
These should be reverted after the dry run to ensure cable->fee agreement again
AIDA09 => AIDA06
AIDA11 => AIDA07
AIDA12 => AIDA08
This will allow the merger to run with 8 FEEs for 1 DSSD
dhcpd.conf updated
The 2023Oct19-13.46.30 should work with this numbering (check tomorrow)
As should layout GSI_triple_test_renumber
AFTER dry run:
Revert DHCP and prepare for full 16 FEEs
Make new ASIC settings key for 16 FEEs and prepare the aidaXX folders
Prepare a new Layout.mlf set |
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539
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Fri Mar 15 16:29:57 2024 |
NH | Leakage currents |
The behaviour of the DSSSD leakage current at low voltages and during biases is unusual and varies depending on how the adapter boards are connected
To summarise the behaviour I have observed
Minimum bias configuration:
4 adapter boards, one n+n (LK1), three p+n (-ve bias), ground from n+n to one p+n
Voltage (and leakage current) unstable at low voltages, seems to settle at around -60 V
Drops can include 0 leakage current
Full adapter configuration:
8 adapter boards, ground ring complete
Same as minimum, but the drops seem to be much smaller (and not to 0 leakage current)
-60V again seems to be the turnover to a stable leakage current
In both cases the leakage current during ramping appears basically the same as when settled
Full into FEEs
8 adapter boards, fully connected to 8 FEEs
The leakage current is *much* higher during ramp,up to 17 uA near the end. No fluctuations
Once ramping has finished the current quickly drops back down and settles at the nominal leakage current
This has been observed in October/December too, it is not new (https://elog.ph.ed.ac.uk/AIDA/910)
During power up of the FEEs the current sometimes drops briefly (when the ASICs get programmed, I believe)
I think it is related to the ground (more or less current flowing through the HV supply instead of alternate paths?)
It should be kept in mind when testing new detectors to not worry about the detector at low voltages |