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ID	Date	Author	Subject
331	Wed May 19 11:24:55 2021	RDP	Monday 19 April 12 noon shift
System checks gave 11 passed/1 failed, except for ADC timimgs: 10 passed/2 failed. FEE64 module aida09 global clocks failed, 6 Clock status test result: Passed 11, Failed 1 Understand status as follows Status bit 3 : firmware PLL that creates clocks from external clock not locked Status bit 2 : always logic '1' Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock If all these bits are not set then the operation of the firmware is unreliable FEE64 module aida07 failed FEE64 module aida09 failed Calibration test result: Passed 10, Failed 2 Base Current Difference aida07 fault 0xd052 : 0xd056 : 4 White Rabbit error counter test result: Passed 11, Failed 1 Understand the status reports as follows:- Status bit 3 : White Rabbit decoder detected an error in the received data Status bit 2 : Firmware registered WR error, no reload of Timestamp Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR Base Current Difference aida12 fault 0x0 : 0x16 : 22 FPGA Timestamp error counter test result: Passed 11, Failed 1 If any of these counts are reported as in error The ASIC readout system has detected a timeslip. That is the timestamp read from the time FIFO is not younger than the last If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module Returned 0 0 0 0 0 0 0 0 0 0 0 0 Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k aida01 : 2 6 2 0 5 5 1 2 3 3 6 : 36120 aida02 : 25 10 0 4 3 5 2 3 3 3 6 : 36980 aida03 : 22 12 5 2 1 3 2 3 3 3 6 : 36616 aida04 : 16 3 3 3 4 4 4 2 3 3 6 : 36840 aida05 : 14 5 6 2 3 4 4 2 3 3 6 : 36800 aida06 : 30 10 6 3 3 4 2 3 3 3 6 : 36936 aida07 : 27 11 1 0 0 3 2 3 3 3 6 : 36436 aida08 : 38 7 7 3 3 2 2 3 3 3 6 : 36704 aida09 : 4 6 4 2 4 4 1 4 3 3 6 : 37056 aida10 : 21 10 3 3 1 5 1 3 3 3 6 : 36596 aida11 : 24 8 2 1 4 3 2 4 2 3 6 : 36192 aida12 : 31 12 4 3 5 5 2 2 3 3 6 : 36668 Collecting the file size of each FEE64 Options CONTENTS file to check they are all the same FEE : aida01 => Options file size is 1025 Last changed Mon Apr 19 10:32:22 CEST 2021 FEE : aida02 => Options file size is 1014 Last changed Fri Apr 16 00:56:20 CEST 2021 FEE : aida03 => Options file size is 1014 Last changed Wed Apr 14 21:52:04 CEST 2021 FEE : aida04 => Options file size is 1025 Last changed Sat Apr 17 06:07:36 CEST 2021 FEE : aida05 => Options file size is 1025 Last changed Fri Apr 16 00:53:25 CEST 2021 FEE : aida06 => Options file size is 1014 Last changed Wed Apr 14 21:52:04 CEST 2021 FEE : aida07 => Options file size is 1014 Last changed Wed Apr 14 21:52:04 CEST 2021 FEE : aida08 => Options file size is 1014 Last changed Wed Apr 14 21:52:04 CEST 2021 FEE : aida09 => Options file size is 1014 Last changed Wed Apr 14 21:52:05 CEST 2021 FEE : aida10 => Options file size is 1014 Last changed Wed Apr 14 21:52:06 CEST 2021 FEE : aida11 => Options file size is 1014 Last changed Wed Apr 14 21:52:05 CEST 2021 FEE : aida12 => Options file size is 1025 Last changed Mon Apr 19 09:05:25 CEST 2021 There should be a separate elog note about changing one of the bias voltages. All histograms zeroed at 16:13. 16.20 DAQ continues file NULL/R33_156 aida09 HEC fast comparator 0x2->0x1 DSSSD#3 bias -100->-120V
Attachment 1: Screenshot_2021-04-19_Temperature_and_status_scan_aidas-gsi(3).png

Attachment 2: Screenshot_2021-04-19_Tape_Service_(Expert)_aidas-gsi.png

Attachment 3: 62.png

610	Fri Apr 26 15:34:00 2024	RDP	16:00 - 00:00 Friday 26 April
This appeared in the system log: Apr 26 16:30:51 aidas-gsi smartd[1076]: Device: /dev/sda [SAT], 1 Currently unreadable (pending) sectors Apr 26 16:30:56 aidas-gsi smartd[1076]: Device: /dev/sdd [SAT], 2224 Currently unreadable (pending) sectors Apr 26 16:30:56 aidas-gsi smartd[1076]: Device: /dev/sdd [SAT], 257 Offline uncorrectable sectors These messages seem to appear sporadically. 18:10 Link 3 is giving rates of zero (see attachment 3). Is this normal? 18:15 daq error on ucesb (attachment 4). Zero rate through event builder. Emailed Nic & can see he's now on Zoom. aida07 rebooted itself, but WR out of sequence still manually reboot aida07, still out of sequence do full powercycle of aida... now all FEEs are in sequence again. Resume running to disk and alert DESPEC shifters Thanks Nic! 22:14 AIDA DSSD 2 HV status = 99 on grafana (attachment 6) 22:43 Noticed that aida02 ASIC temperature reading is now 0.00 instead of 511(!) that it was previously - see attachment 2 in #608. It was similarly high earlier in this shift too.
Attachment 1: Screenshot_2024-04-26_at_16-40-03_ucesb.png

Attachment 2: Screenshot_2024-04-26_at_16-41-57_AIDA_-_Grafana.png

Attachment 3: Screenshot_2024-04-26_at_19-07-21_Merger_Input_Data_Link_Rates_aidas-gsi.png

Attachment 4: Screenshot_2024-04-26_at_19-18-28_ucesb.png

Attachment 5: Screenshot_2024-04-26_at_22-12-06_ucesb.png

Attachment 6: Screenshot_2024-04-26_at_22-11-47_AIDA_-_Grafana.png

313	Thu May 13 19:52:36 2021	Philippos and Marc	Connection problem
At 20:15, We lost connection with AnyDesk. Liliana restarted Anydesk on the AIDA DAQ PC. All seemed fine on AIDA DAQ but there was a more generic issue on the main DAQ, possibly the timesorter. Helena restarted all after ~30mn and it's all working again now.
Attachment 1: 2021-05-13_ucesb_scalers.png

314	Thu May 13 21:21:25 2021	Philippos and Marc	system wide checks
Wide checks at Time 22:22 CET Clock status test result: Passed 16, Failed 0 Understand status as follows Status bit 3 : firmware PLL that creates clocks from external clock not locked Status bit 2 : always logic '1' Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock If all these bits are not set then the operation of the firmware is unreliable FEE64 module aida01 failed FEE64 module aida02 failed FEE64 module aida03 failed FEE64 module aida04 failed FEE64 module aida05 failed FEE64 module aida06 failed FEE64 module aida07 failed FEE64 module aida08 failed FEE64 module aida09 failed FEE64 module aida10 failed FEE64 module aida11 failed FEE64 module aida12 failed FEE64 module aida13 failed FEE64 module aida14 failed FEE64 module aida15 failed FEE64 module aida16 failed Calibration test result: Passed 0, Failed 16 If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module Base Current Difference aida01 fault 0xf932 : 0xf933 : 1 aida02 fault 0x62ec : 0x62ed : 1 aida03 fault 0x8679 : 0x867a : 1 aida04 fault 0xf0e4 : 0xf0e5 : 1 aida05 fault 0x9db8 : 0x9dbc : 4 aida06 fault 0x7f18 : 0x7f19 : 1 aida07 fault 0xdd2c : 0xdd2d : 1 aida08 fault 0x1557 : 0x1558 : 1 White Rabbit error counter test result: Passed 8, Failed 8 Understand the status reports as follows:- Status bit 3 : White Rabbit decoder detected an error in the received data Status bit 2 : Firmware registered WR error, no reload of Timestamp Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR Base Current Difference aida05 fault 0x0 : 0x2 : 2 FPGA Timestamp error counter test result: Passed 15, Failed 1 If any of these counts are reported as in error The ASIC readout system has detected a timeslip. That is the timestamp read from the time FIFO is not younger than the last Returned 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k aida01 : 35 11 3 5 5 4 1 3 2 4 6 : 37876 aida02 : 20 5 4 3 2 5 2 4 3 3 6 : 37400 aida03 : 20 3 4 3 4 4 1 3 2 4 6 : 37640 aida04 : 25 6 2 3 4 4 3 3 3 3 6 : 37140 aida05 : 30 10 5 7 2 6 2 4 2 4 6 : 38776 aida06 : 21 11 4 4 3 5 2 4 3 3 6 : 37548 aida07 : 23 8 4 4 2 6 1 3 2 4 6 : 37852 aida08 : 27 7 2 3 4 3 2 4 3 3 6 : 37284 aida09 : 31 6 5 6 3 3 2 4 3 3 6 : 37372 aida10 : 22 5 3 4 3 6 2 2 2 4 6 : 37616 aida11 : 23 5 4 2 5 2 1 3 2 4 6 : 37444 aida12 : 20 7 4 7 3 5 2 3 3 3 6 : 37096 aida13 : 28 5 3 3 1 5 2 3 3 3 6 : 36840 aida14 : 38 12 2 4 2 4 1 4 3 3 6 : 37144 aida15 : 27 9 5 4 2 5 3 2 3 3 6 : 36740 aida16 : 21 6 4 4 1 4 2 3 3 3 6 : 36740
Attachment 1: 2021-05-13_ucesb_scalers_22h22mn.png

Attachment 2: 2021-05-13_Currents_22h22mn.png

Attachment 3: 2021-05-13_temperatures_22h22.png

Attachment 4: 2021-05-13-22h22mn_Stat-good-events.png

Attachment 5: 2021-05-13-22h22mn_ADC-data-items.png

Attachment 6: 2021-05-13_22h22mn-Correlation-info.png

Attachment 7: 2021-05-13_22h22mn-Pause-info.png

Attachment 8: 2021-05-13_22h22mn-Resume-Info.png

Attachment 9: 2021-05-13_merger_22h22.png

Attachment 10: 2021-05-13_22h22mn-LAY-ID1.png

Attachment 11: 2021-05-13_22h22mn-LAY-ID2.png

Attachment 12: 2021-05-13_22h22mn-LAY-ID3.png

Attachment 13: 2021-05-13_22h22mn-LAY-ID4.png

494	Thu Jun 23 15:10:17 2022	Philippos Papadakis	Thursday 23 June 16:00-24:00
16:20 System wide checks. Clock status OK White Rabbit Error status: Base Current Difference aida07 fault 0xc4fe : 0xc525 : 39 aida08 fault 0xf0e9 : 0xf166 : 125 White Rabbit error counter test result: Passed 6, Failed 2 FPGA error status: Base Current Difference aida07 fault 0x11 : 0x1c : 11 aida08 fault 0x1a : 0x23 : 9 Temps OK (attachment 1), Stats OK (attachment 2), Bias and leakage OK (attachment 3) 18:05 System wide checks. Clock status OK White Rabbit Error status: Base Current Difference aida07 fault 0xc4fe : 0xc527 : 41 aida08 fault 0xf0e9 : 0xf177 : 142 White Rabbit error counter test result: Passed 6, Failed 2 FPGA error status: Base Current Difference aida07 fault 0x11 : 0x1c : 11 aida08 fault 0x1a : 0x24 : 10 FPGA Timestamp error counter test result: Passed 6, Failed 2 Temps OK (attachment 4), Stats OK (attachment 5), Bias and leakage OK (attachment 6) 20:22 System wide checks. Clock status OK White Rabbit Error status: Base Current Difference aida07 fault 0xc4fe : 0xc529 : 43 aida08 fault 0xf0e9 : 0xf17f : 150 White Rabbit error counter test result: Passed 6, Failed 2 FPGA error status: Base Current Difference aida07 fault 0x11 : 0x20 : 15 aida08 fault 0x1a : 0x25 : 11 FPGA Timestamp error counter test result: Passed 6, Failed 2 Temps OK (attachment 7), Stats OK (attachment 8), Bias and leakage OK (attachment 9) 21:56 System wide checks. Clock status OK White Rabbit Error status: Base Current Difference aida07 fault 0xc4fe : 0xc529 : 43 aida08 fault 0xf0e9 : 0xf186 : 157 White Rabbit error counter test result: Passed 6, Failed 2 FPGA error status: Base Current Difference aida07 fault 0x11 : 0x21 : 16 aida08 fault 0x1a : 0x26 : 12 Temps OK (attachment 10), Stats OK (attachment 11), Bias and leakage OK (attachment 12) 23:50 System wide checks. Clock status OK White Rabbit Error status: Base Current Difference aida07 fault 0xc4fe : 0xc52e : 48 aida08 fault 0xf0e9 : 0xf18c : 163 White Rabbit error counter test result: Passed 6, Failed 2 FPGA error status: Base Current Difference aida07 fault 0x11 : 0x21 : 16 aida08 fault 0x1a : 0x27 : 13 FPGA Timestamp error counter test result: Passed 6, Failed 2 Temps OK (attachment 13), Stats OK (attachment 14), Bias and leakage OK (attachment 15)
Attachment 1: Temperatures_2022-06-23_16-14-38.png

Attachment 2: stats_2022-06-23_16-16-30.png

Attachment 3: IV2022-06-23_16-17-13.png

Attachment 4: Temps_2022-06-23_18-08-04.png

Attachment 5: Stats_2022-06-23_18-08-38.png

Attachment 6: IV_2022-06-23_18-09-41.png

Attachment 7: Temps_2022-06-23_20-24-48.png

Attachment 8: Stats_2022-06-23_20-25-18.png

Attachment 9: IV2022-06-23_20-25-39.png

Attachment 10: Temps_2022-06-23_21-59-26.png

Attachment 11: Stats_2022-06-23_22-00-01.png

Attachment 12: IV_2022-06-23_22-00-20.png

Attachment 13: Temps_2022-06-23_23-52-04.png

Attachment 14: Stats_2022-06-23_23-52-32.png

Attachment 15: IV_2022-06-23_23-52-50.png

78	Thu Oct 31 19:02:42 2019	Patrick	WR Timestamps
> All 12 FEEs have valid WR Timestamps > Had to powercycle aida09 once as before raw readout was displaying upper 12 bits of WR timestamp as 0. Unsure of other method. > > HDMI cables in aida09 checked and good. The problem would be the cable , one end or the other. I think ( if I recall ) a setup would restart the WR decoder. I notice you have set the WR info word rate to be quite high , 6123/sec typ, is this intentional ?
651	Tue Jun 11 15:01:07 2024	PP TD	16:00-00:00 shift Tuesday 11/06/24
All seems OK Screenshots attached. 17.33 per FEE64 1.8.W spectra - attachments 8-9 per p+n FEE64 1.8.L spectra - attachment 10 aida09 pulser peak width 66 ch FWHM cf c. 11:00 today 57 ch FWHM https://elog.ph.ed.ac.uk/DESPEC/650 cf c. 00:10 today 53 ch FWHM https://elog.ph.ed.ac.uk/DESPEC/649 17.48 ADC data item stats - attachment 11 All histograms zero'd 17.51 Analysis data file S181/R6_96 - attachment 12 max deadtime 5% (aida08) HEC Data items 3.7kHz, LEC data items 1.8MHz cf. c. 12.29 today 1.1MHz https://elog.ph.ed.ac.uk/DESPEC/650 c. 00.09 today 1.1MHz https://elog.ph.ed.ac.uk/DESPEC/649
Attachment 1: Screenshot_from_2024-06-11_16-06-43.png

Attachment 2: Screenshot_from_2024-06-11_16-07-53.png

Attachment 3: Screenshot_from_2024-06-11_16-09-03.png

Attachment 4: Screenshot_from_2024-06-11_16-12-05.png

Attachment 5: Screenshot_from_2024-06-11_16-12-46.png

Attachment 6: Screenshot_from_2024-06-11_16-13-40.png

Attachment 7: Screenshot_from_2024-06-11_16-14-11.png

Attachment 8: Screenshot_from_2024-06-11_16-17-21.png

Attachment 9: Screenshot_from_2024-06-11_17-34-26.png

Attachment 10: Screenshot_from_2024-06-11_17-33-33.png

Attachment 11: Screenshot_from_2024-06-11_17-39-32.png

Attachment 12: Screenshot_from_2024-06-11_17-48-43.png

Attachment 13: R6_98
* TDR format 3.3.0 analyser - TD - May 2021 * ERROR: READ I/O error: 5002 blocks: 32000 ADC data format: 258260025 ( 1785474.1 Hz) Other data format: 3659975 ( 25303.1 Hz) Sample trace data format: 0 ( 0.0 Hz) Undefined format: 0 ( 0.0 Hz) Other data format type: PAUSE: 939 ( 6.5 Hz) RESUME: 938 ( 6.5 Hz) SYNC100: 32538 ( 225.0 Hz) WR48-63: 32538 ( 225.0 Hz) FEE64 disc: 0 ( 0.0 Hz) MBS info: 3593022 ( 24840.3 Hz) Other info: 0 ( 0.0 Hz) ADC data range bit set: 539819 ( 3732.0 Hz) Timewarps: ADC: 0 ( 0.0 Hz) PAUSE: 0 ( 0.0 Hz) RESUME: 0 ( 0.0 Hz) SYNC100: 0 ( 0.0 Hz) WR48-63: 0 ( 0.0 Hz) FEE64 disc: 0 ( 0.0 Hz) MBS info: 0 ( 0.0 Hz) Undefined: 0 ( 0.0 Hz) Sample trace: 0 ( 0.0 Hz) * Timestamp elapsed time: 144.645 s FEE elapsed dead time(s) elapsed idle time(s) 0 0.468 0.000 1 0.015 0.000 2 0.040 0.000 3 0.872 0.000 4 0.007 0.000 5 0.312 0.000 6 0.000 0.000 7 7.299 0.000 8 0.001 0.000 9 3.731 0.000 10 2.112 0.000 11 0.008 0.000 12 0.000 0.000 13 0.367 0.000 14 0.001 0.000 15 1.636 0.000 16 0.000 0.000 17 0.000 0.000 18 0.000 0.000 19 0.000 0.000 20 0.000 0.000 21 0.000 0.000 22 0.000 0.000 23 0.000 0.000 24 0.000 0.000 25 0.000 0.000 26 0.000 0.000 27 0.000 0.000 28 0.000 0.000 29 0.000 0.000 30 0.000 0.000 31 0.000 0.000 32 0.000 0.000 * Statistics FEE ADC Data Other Data Sample Undefined Pause Resume SYNC100 WR48-63 Disc MBS Other HEC Data 0 15794317 8531 0 0 49 49 2058 2058 0 4317 0 10696 1 7121332 1752 0 0 3 3 873 873 0 0 0 24880 2 15560192 1259782 0 0 6 6 2078 2078 0 1255614 0 14645 3 17271150 4664 0 0 134 134 2198 2198 0 0 0 19004 4 6664272 367237 0 0 2 2 840 840 0 365553 0 5226 5 16529211 4220 0 0 48 48 2062 2062 0 0 0 23130 6 5459932 300460 0 0 0 0 680 680 0 299100 0 14450 7 45345978 11675 0 0 200 199 5638 5638 0 0 0 336191 8 6229388 1534 0 0 1 1 766 766 0 0 0 16825 9 38606423 1232596 0 0 155 155 5043 5043 0 1222200 0 15969 10 19820101 5140 0 0 195 195 2375 2375 0 0 0 9560 11 4555885 447544 0 0 2 2 651 651 0 446238 0 14419 12 4015114 976 0 0 0 0 488 488 0 0 0 3706 13 15417116 3872 0 0 46 46 1890 1890 0 0 0 14088 14 5845488 1420 0 0 1 1 709 709 0 0 0 10117 15 34024126 8572 0 0 97 97 4189 4189 0 0 0 6913 16 0 0 0 0 0 0 0 0 0 0 0 0 17 0 0 0 0 0 0 0 0 0 0 0 0 18 0 0 0 0 0 0 0 0 0 0 0 0 19 0 0 0 0 0 0 0 0 0 0 0 0 20 0 0 0 0 0 0 0 0 0 0 0 0 21 0 0 0 0 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 0 0 23 0 0 0 0 0 0 0 0 0 0 0 0 24 0 0 0 0 0 0 0 0 0 0 0 0 25 0 0 0 0 0 0 0 0 0 0 0 0 26 0 0 0 0 0 0 0 0 0 0 0 0 27 0 0 0 0 0 0 0 0 0 0 0 0 28 0 0 0 0 0 0 0 0 0 0 0 0 29 0 0 0 0 0 0 0 0 0 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 31 0 0 0 0 0 0 0 0 0 0 0 0 32 0 0 0 0 0 0 0 0 0 0 0 0 * Timewarps FEE ADC Pause Resume SYNC100 WR48-63 Disc MBS Undefined Samples 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 7 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 11 0 0 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 13 0 0 0 0 0 0 0 0 0 14 0 0 0 0 0 0 0 0 0 15 0 0 0 0 0 0 0 0 0 16 0 0 0 0 0 0 0 0 0 17 0 0 0 0 0 0 0 0 0 18 0 0 0 0 0 0 0 0 0 19 0 0 0 0 0 0 0 0 0 20 0 0 0 0 0 0 0 0 0 21 0 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 23 0 0 0 0 0 0 0 0 0 24 0 0 0 0 0 0 0 0 0 25 0 0 0 0 0 0 0 0 0 26 0 0 0 0 0 0 0 0 0 27 0 0 0 0 0 0 0 0 0 28 0 0 0 0 0 0 0 0 0 29 0 0 0 0 0 0 0 0 0 30 0 0 0 0 0 0 0 0 0 31 0 0 0 0 0 0 0 0 0 32 0 0 0 0 0 0 0 0 0 * Program elapsed time: 36.520s ( 876.243 blocks/s, 54.765 Mb/s)
446	Sat May 14 03:14:00 2022	PP	Shift Checks
4:13 AIDA stats OK Leakage current OK Temperatures OK grafana OK ucesb rates OK System wide check done and same results as earlier: aida09 fails clock (1), aida02 06 09 10 13 fail ADC calibration, all pass WR Screenshot 1: statistics Screenshot 2: temperatures Screenshot 3: scalers Screenshot 4: Bias and leakage current 6:36 AIDA stats OK Leakage current OK Temperatures OK grafana OK ucesb rates OK System wide check done and same results as earlier: aida09 fails clock (1), aida02 06 09 10 13 fail ADC calibration, all pass WR Screenshot 5: statistics Screenshot 6: temperatures Screenshot 7: scalers Screenshot 8: Bias and leakage current
Attachment 1: stats-220514-0428.png

Attachment 2: temps-220514-0417.png

Attachment 3: scalers-220514-0426.png

Attachment 4: I-V-220514-0431.png

Attachment 5: stats-220514-0639.png

Attachment 6: temps-220514-0639.png

Attachment 7: scalers-220514-0641.png

Attachment 8: I-V-220514-0640.png

590	Tue Apr 23 07:27:18 2024	PP	08:00-16:00 Tuesday 24 April shift
Checks 08:00-08:30 Screenshots are attached and everything looks OK.
Attachment 1: Screenshot_from_2024-04-23_08-10-21.png

Attachment 2: Screenshot_from_2024-04-23_08-13-20.png

Attachment 3: Screenshot_from_2024-04-23_08-15-30.png

Attachment 4: Screenshot_from_2024-04-23_08-18-28.png

Attachment 5: Screenshot_from_2024-04-23_08-23-07.png

Attachment 6: Screenshot_from_2024-04-23_08-26-31.png

Attachment 7: Screenshot_from_2024-04-23_08-35-31.png

Attachment 8: Screenshot_from_2024-04-23_08-39-43.png

591	Tue Apr 23 09:21:01 2024	PP	10:20 checks - aida02 is down
Aida02 is down. Contacted Nick. The rest looks stable, see screenshots. 10:53 CEST (NH): Rebooted aida02 via telnet Resync ASIC clocks All system wide checks look ok ASIC threshold => 0x14 Go > All 16 writing to merger, looks OK aida02 went down again 11:35 CEST Rebooted with same procedure and is back again
Attachment 1: Screenshot_from_2024-04-23_10-08-54.png

Attachment 2: Screenshot_from_2024-04-23_10-13-23.png

Attachment 3: Screenshot_from_2024-04-23_10-15-28.png

Attachment 4: Screenshot_from_2024-04-23_10-16-23.png

Attachment 5: Screenshot_from_2024-04-23_10-16-47.png

Attachment 6: Screenshot_from_2024-04-23_10-17-47.png

Attachment 7: Screenshot_from_2024-04-23_10-19-30.png

Attachment 8: Screenshot_from_2024-04-23_10-20-20.png

592	Tue Apr 23 10:10:31 2024	PP	aida02 is back
Nick rebooted AIDA and aida02 came back at around 10:55. AIDA was out of the DAQ from about 10:30 until 10:55
593	Tue Apr 23 10:52:39 2024	PP	Aida02 down and back
We lost aida02 at about 11:25 again. Nick fixed it about 11:50. It is now back in the DAQ.
594	Tue Apr 23 11:09:00 2024	PP	12:00 checks
Everything is OK now. Screenshots attached.
Attachment 1: Screenshot_from_2024-04-23_12-01-49.png

Attachment 2: Screenshot_from_2024-04-23_12-02-24.png

Attachment 3: Screenshot_from_2024-04-23_12-03-36.png

Attachment 4: Screenshot_from_2024-04-23_12-04-05.png

Attachment 5: Screenshot_from_2024-04-23_12-05-52.png

Attachment 6: Screenshot_from_2024-04-23_12-06-42.png

Attachment 7: Screenshot_from_2024-04-23_12-07-41.png

Attachment 8: Screenshot_from_2024-04-23_12-08-32.png

597	Tue Apr 23 13:15:43 2024	PP	14:00 checks
All looks good. Screenshots attached
Attachment 1: Screenshot_from_2024-04-23_14-11-33.png

Attachment 2: Screenshot_from_2024-04-23_14-04-26.png

Attachment 3: Screenshot_from_2024-04-23_14-04-44.png

Attachment 4: Screenshot_from_2024-04-23_14-06-02.png

Attachment 5: Screenshot_from_2024-04-23_14-07-07.png

Attachment 6: Screenshot_from_2024-04-23_14-09-26.png

Attachment 7: Screenshot_from_2024-04-23_14-10-55.png

Attachment 8: Screenshot_from_2024-04-23_14-11-16.png

599	Tue Apr 23 19:23:42 2024	PP	20:30 checks
All looks good. Screenshots attached.
Attachment 1: Screenshot_from_2024-04-23_20-24-09.png

Attachment 2: Screenshot_from_2024-04-23_20-24-25.png

Attachment 3: Screenshot_from_2024-04-23_20-24-52.png

Attachment 4: Screenshot_from_2024-04-23_20-25-35.png

Attachment 5: Screenshot_from_2024-04-23_20-26-16.png

Attachment 6: Screenshot_from_2024-04-23_20-27-01.png

Attachment 7: Screenshot_from_2024-04-23_20-27-26.png

Attachment 8: Screenshot_from_2024-04-23_20-27-53.png

602	Wed Apr 24 15:37:59 2024	PP	16:00-00:00 shift Wednesday 24 April
All seems OK. Screenshots attached.
Attachment 1: Screenshot_from_2024-04-24_16-38-45.png

Attachment 2: Screenshot_from_2024-04-24_16-39-09.png

Attachment 3: Screenshot_from_2024-04-24_16-39-38.png

Attachment 4: Screenshot_from_2024-04-24_16-40-24.png

Attachment 5: Screenshot_from_2024-04-24_16-41-15.png

Attachment 6: Screenshot_from_2024-04-24_16-43-41.png

Attachment 7: Screenshot_from_2024-04-24_16-44-15.png

Attachment 8: Screenshot_from_2024-04-24_16-44-32.png

603	Wed Apr 24 18:44:05 2024	PP	19:30 checks
All seems smooth. Screenshots attached.
Attachment 1: Screenshot_from_2024-04-24_19-34-58.png

Attachment 2: Screenshot_from_2024-04-24_19-37-12.png

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Attachment 8: Screenshot_from_2024-04-24_19-43-41.png

652	Tue Jun 11 18:45:37 2024	PP	Mid-shift checks, 19:45
All looks good. Sceenshots attached.
Attachment 1: Screenshot_from_2024-06-11_19-46-41.png

Attachment 2: Screenshot_from_2024-06-11_19-47-09.png

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656	Wed Jun 12 11:06:55 2024	PP	Mid-shift checks, 12:00
All seems normal. Screenshots attached.
Attachment 1: Screenshot_from_2024-06-12_12-07-32.png

Attachment 2: Screenshot_from_2024-06-12_12-07-59.png

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517	Wed Jan 18 13:40:33 2023	PJCS TD	MACB settings with either Emulator or VITAR
When using the VETAR connected to the HDMI port of the root MACB the settings for all the MACB in the system 0x3. This setting takes the Clock and Data line from the input HDMI and outputs it via teh HDMI output ports. When using the Emulator connected via the SMA connectors on the back of the root MACB then the setting for the root MACB should be 0xD and all others should be 0x3. Attached is the .jed file for programming the MACB and the .vhd source file to help with understanding of the settings.
Attachment 1: macb_apr20.jed
Attachment 2: macb_apr20.vhd
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 17:03:27 03/16/2011 -- Design Name: -- Module Name: macb_top - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; -- NOTE all in/out notations are relative to this unit entity macb_apr20 is Port ( port1_sp : inout STD_LOGIC_VECTOR (3 downto 0); port2_sp : inout STD_LOGIC_VECTOR (3 downto 0); port3_sp : inout STD_LOGIC_VECTOR (3 downto 0); port4_sp : inout STD_LOGIC_VECTOR (3 downto 0); layer_sp : inout STD_LOGIC_VECTOR (3 downto 0); layer_trigger : out std_logic ; sync_return : in STD_LOGIC_VECTOR (3 downto 1); selector : in STD_LOGIC_VECTOR (3 downto 0); sync_select : out STD_LOGIC_vector(1 downto 0 ); clock200_select : out STD_LOGIC_vector( 1 downto 0 ) ; butis_divide_reset : out std_logic ; butis_divide_s : out std_logic_vector( 2 downto 0 ) ; clock_5 : in std_logic ; sync_5 : in std_logic ; trigger : in std_logic_vector( 3 downto 0 ) ; MBS_in : in STD_LOGIC_VECTOR (3 downto 0); MBS_out : out STD_LOGIC_VECTOR (3 downto 0)); end macb_apr20; architecture Behavioral of macb_apr20 is signal port1_spi : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' ); signal port1_spo : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' ); signal port1_t : STD_LOGIC_VECTOR (3 downto 0) := ( others => '1' ); signal port2_spi : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' ); signal port2_spo : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' ); signal port2_t : STD_LOGIC_VECTOR (3 downto 0) := ( others => '1' ); signal port3_spi : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' ); signal port3_spo : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' ); signal port3_t : STD_LOGIC_VECTOR (3 downto 0) := ( others => '1' ); signal port4_spi : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' ); signal port4_spo : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' ); signal port4_t : STD_LOGIC_VECTOR (3 downto 0) := ( others => '1' ); signal layer_spi : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' ); signal layer_spo : STD_LOGIC_VECTOR (3 downto 0) := ( others => '0' ); signal layer_t : STD_LOGIC_VECTOR (3 downto 0) := ( others => '1' ); signal seli : integer range 0 to 15 := 0 ; -- well really signal MBS_in_n : std_logic_vector( 3 downto 0 ) := "0000" ; begin MBS_in_n <= ( not MBS_in); seli <= conv_integer(not selector) ; -- MBS signal allocations to sp lines and HDMI pin. This maps to NIM connections -- 0 : MBS_clock10 SP0 13 -- 1 : MBS_reset SP1 14 -- 2 : MBS_reset_rq SP2 15 -- 3 : MBS_Trigger SP3 16 layer_trigger <= trigger(0) or trigger(1) or trigger(2) or trigger(3) ; -- divider controls set for pass-through butis_divide_reset <= '1' ; -- for now don't reset ; process ( seli , MBS_in_n, port1_spi, port2_spi, port3_spi, port4_spi, layer_spi, sync_return ,sync_5 ) -- note : & => concatenate begin case seli is when 0 => --- Master/ Root / MBS / Internal clock port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ; port1_t <= "0011" ; -- drive trigger and reset request only port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ; port2_t <= "0100" ; -- drive clock, reset, trigger only port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ; port3_t <= "0100" ; -- drive clock, reset, trigger only port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ; port4_t <= "0100" ; -- drive clock, reset, trigger only layer_spo <= ( others => '0' ) ; layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port sync_select <= "00" ; -- select sync from port 1 clock200_select <= "00" ; -- select internal 200 MHz oscillator MBS_out <= MBS_in_n(3) & MBS_in_n(2) & port1_spi(1) & port1_spi(0) ; butis_divide_s <= "000" ; -- s2 is 0 for pass, when 1 => --- Master/ Root / MBS / BuTiS clock and SYNC port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ; port1_t <= "0011" ; -- drive trigger and reset request only port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ; port2_t <= "0100" ; -- drive clock, reset, trigger only port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ; port3_t <= "0100" ; -- drive clock, reset, trigger only port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ; port4_t <= "0100" ; -- drive clock, reset, trigger only layer_spo <= ( others => '0' ) ; layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port sync_select <= "01" ; -- select sync from external using SMA input clock200_select <= "01" ; -- select external 200 MHz oscillator using SMA input MBS_out <= MBS_in_n(3) & MBS_in_n(2) & port1_spi(1) & port1_spi(0) ; butis_divide_s <= "000" ; -- s2 is 0 for pass, when 2 => --- Master/ Branch / MBS / Next layer clock next layer SYNC port1_spo <= layer_spi(3) & layer_spi(2) & '0' & '0' ; port1_t <= "0011" ; -- drive trigger and reset request only port2_spo <= layer_spi(3) & '0' & port1_spi(1) & port1_spi(0) ; port2_t <= "0100" ; -- drive clock, reset, trigger only port3_spo <= layer_spi(3) & '0' & port1_spi(1) & port1_spi(0) ; port3_t <= "0100" ; -- drive clock, reset, trigger only port4_spo <= layer_spi(3) & '0' & port1_spi(1) & port1_spi(0) ; port4_t <= "0100" ; -- drive clock, reset, trigger only layer_spo <= '0' & '0' & port1_spi(1) & port1_spi(0) ; -- drive the clock and reset down a layer layer_t <= "1100" ; -- just drive the bottom two bits to the "next" port sync_select <= "10" ; -- select sync from next_layer clock200_select <= "10" ; -- select clock from next layer MBS_out <= layer_spi(3) & layer_spi(2) & port1_spi(1) & port1_spi(0) ; butis_divide_s <= "000" ; -- s2 is 0 for pass, when 3 => --- Slave / Branch / MBS / Next layer clock and sync port1_spo <= layer_spi(3) & '0' & layer_spi(1) & layer_spi(0); port1_t <= "0100" ; -- drive clock, reset, trigger only port2_spo <= layer_spi(3) & '0' & layer_spi(1) & layer_spi(0) ; port2_t <= "0100" ; -- drive clock, reset, trigger only port3_spo <= layer_spi(3) & '0' & layer_spi(1) & layer_spi(0) ; port3_t <= "0100" ; -- drive clock, reset, trigger only port4_spo <= layer_spi(3) & '0' & layer_spi(1) & layer_spi(0) ; port4_t <= "0100" ; -- drive clock, reset, trigger only layer_spo <= '0' & '0' & '0' & '0' ; -- drive nothing layer_t <= "1111" ; -- just drive nothing down sync_select <= "10" ; -- select sync from next layer clock200_select <= "10" ; -- select clock from next layer MBS_out <= layer_spi ; -- map all the signals for monitoring ? butis_divide_s <= "000" ; -- s2 is 0 for pass, when 4 => --- Master/ Root / MBS / BuTiS clock / Internal SYNC / External timestamp reset port1_spo <= MBS_in_n(3) & '0' & MBS_in_n(1) & '0' ; port1_t <= "0100" ; -- drive clock, reset, trigger only port2_spo <= MBS_in_n(3) & '0' & MBS_in_n(1) & '0' ; port2_t <= "0100" ; -- drive clock, reset, trigger only port3_spo <= MBS_in_n(3) & '0' & MBS_in_n(1) & '0' ; port3_t <= "0100" ; -- drive clock, reset, trigger only port4_spo <= MBS_in_n(3) & '0' & MBS_in_n(1) & '0' ; port4_t <= "0100" ; -- drive clock, reset, trigger only layer_spo <= ( others => '0' ) ; layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port sync_select <= "00" ; -- select sync from port 1 clock200_select <= "01" ; -- select external 50 MHz oscillator using SMA input MBS_out <= MBS_in_n(3) & MBS_in_n(2) & MBS_in_n(1) & sync_5 ; butis_divide_s <= "000" ; -- s2 is 0 for pass, when 5 => --- Master/ Root / MBS / External 50Mhz clock / Internal Sync port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ; port1_t <= "0011" ; -- drive trigger and reset request only port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ; port2_t <= "0100" ; -- drive clock, reset, trigger only port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ; port3_t <= "0100" ; -- drive clock, reset, trigger only port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ; port4_t <= "0100" ; -- drive clock, reset, trigger only layer_spo <= ( others => '0' ) ; layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port sync_select <= "00" ; -- select sync from port 1 clock200_select <= "01" ; -- select external SMA input MBS_out <= MBS_in_n(3) & MBS_in_n(2) & port1_spi(1) & port1_spi(0) ; butis_divide_s <= "000" ; -- s2 is 0 for pass through. when 6 => --- Master/ Root / MBS / External 100Mhz clock / Internal Sync port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ; port1_t <= "0011" ; -- drive trigger and reset request only port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ; port2_t <= "0100" ; -- drive clock, reset, trigger only port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ; port3_t <= "0100" ; -- drive clock, reset, trigger only port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ; port4_t <= "0100" ; -- drive clock, reset, trigger only layer_spo <= ( others => '0' ) ; layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port sync_select <= "00" ; -- select sync from port 1 clock200_select <= "01" ; -- select external SMA input MBS_out <= MBS_in_n(3) & MBS_in_n(2) & port1_spi(1) & port1_spi(0) ; butis_divide_s <= "100" ; -- s2 is 1 for external, 00 for /2. when 7 => --- Fast NIM input for each FEE / Next layer clock next layer SYNC port1_spo <= MBS_in_n(0) & layer_spi(2) & '0' & '0' ; port1_t <= "0011" ; -- drive trigger and reset request only port2_spo <= MBS_in_n(1) & '0' & port1_spi(1) & port1_spi(0) ; port2_t <= "0100" ; -- drive clock, reset, trigger only port3_spo <= MBS_in_n(2) & '0' & port1_spi(1) & port1_spi(0) ; port3_t <= "0100" ; -- drive clock, reset, trigger only port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ; port4_t <= "0100" ; -- drive clock, reset, trigger only layer_spo <= '0' & '0' & port1_spi(1) & port1_spi(0) ; -- drive the clock and reset down a layer layer_t <= "1100" ; -- just drive the bottom two bits to the "next" port sync_select <= "10" ; -- select sync from next_layer clock200_select <= "10" ; -- select clock from next layer MBS_out <= layer_spi(3) & layer_spi(2) & port1_spi(1) & port1_spi(0) ; butis_divide_s <= "000" ; -- s2 is 0 for pass, when 8 => --- Fast NIM input from Input 3 for each FEE / Next layer clock next layer SYNC port1_spo <= MBS_in_n(3) & layer_spi(2) & '0' & '0' ; port1_t <= "0011" ; -- drive trigger and reset request only port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ; port2_t <= "0100" ; -- drive clock, reset, trigger only port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ; port3_t <= "0100" ; -- drive clock, reset, trigger only port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ; port4_t <= "0100" ; -- drive clock, reset, trigger only layer_spo <= '0' & '0' & port1_spi(1) & port1_spi(0) ; -- drive the clock and reset down a layer layer_t <= "1100" ; -- just drive the bottom two bits to the "next" port sync_select <= "10" ; -- select sync from next_layer clock200_select <= "10" ; -- select clock from next layer MBS_out <= layer_spi(3) & layer_spi(2) & port1_spi(1) & port1_spi(0) ; butis_divide_s <= "000" ; -- s2 is 0 for pass, when 9 => --- Master/ Root / Internal clock / sync_returns to NIM port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ; port1_t <= "0011" ; -- drive trigger and reset request only port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ; port2_t <= "0100" ; -- drive clock, reset, trigger only port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ; port3_t <= "0100" ; -- drive clock, reset, trigger only port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ; port4_t <= "0100" ; -- drive clock, reset, trigger only layer_spo <= ( others => '0' ) ; layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port sync_select <= "00" ; -- select sync from port 1 clock200_select <= "00" ; -- select internal 200 MHz oscillator MBS_out <= sync_return(3) & sync_return(2) & sync_return(1) & '0' ; butis_divide_s <= "000" ; -- s2 is 0 for pass, when 10 => --- Master/ Root / MBS / BuTiS clock /2 and SYNC port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ; port1_t <= "0011" ; -- drive trigger and reset request only port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ; port2_t <= "0100" ; -- drive clock, reset, trigger only port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ; port3_t <= "0100" ; -- drive clock, reset, trigger only port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ; port4_t <= "0100" ; -- drive clock, reset, trigger only layer_spo <= "0000" ; layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port sync_select <= "01" ; -- select sync from external using SMA input clock200_select <= "01" ; -- select external 200 MHz oscillator using SMA input MBS_out <= MBS_in_n ; -- for testing NIM I/O butis_divide_s <= "100" ; -- s2 = 1 and s1,s0 decode to 00=>/2 , 01=>/4, /8 , /16 when 12 => --- Master/ Root / MBS / BuTiS clock /2 and SYNC port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ; port1_t <= "0011" ; -- drive trigger and reset request only port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ; port2_t <= "0100" ; -- drive clock, reset, trigger only port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ; port3_t <= "0100" ; -- drive clock, reset, trigger only port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ; port4_t <= "0100" ; -- drive clock, reset, trigger only layer_spo <= ( others => '0' ) ; layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port sync_select <= "01" ; -- select sync from external using SMA input clock200_select <= "01" ; -- select external 200 MHz oscillator using SMA input MBS_out <= MBS_in_n(3) & MBS_in_n(2) & port1_spi(1) & port1_spi(0) ; butis_divide_s <= "100" ; -- s2 = 1 and s1,s0 decode to 00=>/2 , 01=>/4, /8 , /16 when 13 => --- Master/ Root / MBS / BuTiS clock /4 and SYNC port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ; port1_t <= "0011" ; -- drive trigger and reset request only port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ; port2_t <= "0100" ; -- drive clock, reset, trigger only port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ; port3_t <= "0100" ; -- drive clock, reset, trigger only port4_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ; port4_t <= "0100" ; -- drive clock, reset, trigger only layer_spo <= ( others => '0' ) ; layer_t <= ( others => '1' ) ; -- disable the drive to the "next" port sync_select <= "01" ; -- select sync from external using SMA input clock200_select <= "01" ; -- select external 200 MHz oscillator using SMA input MBS_out <= MBS_in_n(3) & MBS_in_n(2) & port1_spi(1) & port1_spi(0) ; butis_divide_s <= "101" ; -- s2 = 1 and s1,s0 decode to 01=>/4 when 14 => --- Master/ Root / MBS / BuTiS clock /8 and SYNC port1_spo <= MBS_in_n(3) & MBS_in_n(2) & '0' & '0' ; port1_t <= "0011" ; -- drive trigger and reset request only port2_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ; port2_t <= "0100" ; -- drive clock, reset, trigger only port3_spo <= MBS_in_n(3) & '0' & port1_spi(1) & port1_spi(0) ; ... 161 more lines ...
Attachment 3: zybo.jpg

Attachment 4: MACB.jpg

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ELOG V3.1.4-unknown