ELOG DESPEC

AIDA GELINA BRIKEN nToF CRIB ISOLDE CIRCE nTOFCapture DESPEC DTAS EDI_PSA 179Ta CARME StellarModelling DCF K40

DESPEC, Page 35 of 35

Full | Summary | Threaded | Hide attachments

691 Entries

Goto page Previous 1, 2, 3 ... 33, 34, 35

ID	Date	Author	Subject
451	Sat May 14 15:35:24 2022	BA, AA	Saturday 14 May

Attachment 1: Stais_from_2022-05-14_16-30-53.png

Attachment 2: Temp_2022-05-14_16-32-42.png

Attachment 3: Leakage_2022-05-14_16-33-45.png

452	Sat May 14 17:34:40 2022	BA, AA	Saturday 14 May
FEE64 module aida09 global clocks failed, 6 Clock status test result: Passed 13, Failed 1 Understand status as follows Status bit 3 : firmware PLL that creates clocks from external clock not locked Status bit 2 : always logic '1' Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock If all these bits are not set then the operation of the firmware is unreliable FEE64 module aida02 failed FEE64 module aida06 failed FEE64 module aida09 failed FEE64 module aida10 failed FEE64 module aida13 failed Calibration test result: Passed 9, Failed 5 If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module White Rabbit error counter test result: Passed 14, Failed 0 Understand the status reports as follows:- Status bit 3 : White Rabbit decoder detected an error in the received data Status bit 2 : Firmware registered WR error, no reload of Timestamp Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR FPGA Timestamp error counter test result: Passed 14, Failed 0 If any of these counts are reported as in error The ASIC readout system has detected a timeslip. That is the timestamp read from the time FIFO is not younger than the last
Attachment 1: Stat_2022-05-14_18-33-16.png

Attachment 2: Temp_2022-05-14_18-32-07.png

Attachment 3: Leakage_2022-05-14_18-30-52.png

453	Sat May 14 19:39:13 2022	BA, AA	Saturday 14 May
FEE64 module aida09 global clocks failed, 6 Clock status test result: Passed 13, Failed 1 Understand status as follows Status bit 3 : firmware PLL that creates clocks from external clock not locked Status bit 2 : always logic '1' Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock If all these bits are not set then the operation of the firmware is unreliable FEE64 module aida02 failed FEE64 module aida06 failed FEE64 module aida09 failed FEE64 module aida10 failed FEE64 module aida13 failed Calibration test result: Passed 9, Failed 5 If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module White Rabbit error counter test result: Passed 14, Failed 0 Understand the status reports as follows:- Status bit 3 : White Rabbit decoder detected an error in the received data Status bit 2 : Firmware registered WR error, no reload of Timestamp Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR FPGA Timestamp error counter test result: Passed 14, Failed 0 If any of these counts are reported as in error The ASIC readout system has detected a timeslip. That is the timestamp read from the time FIFO is not younger than the last
Attachment 1: Stat_2022-05-14_20-36-15.png

Attachment 2: Temp_2022-05-14_20-35-19.png

Attachment 3: Leakage_2022-05-14_20-33-32.png

454	Sat May 14 21:34:11 2022	BA, AA	Saturday 14 May
FEE64 module aida09 global clocks failed, 6 Clock status test result: Passed 13, Failed 1 Understand status as follows Status bit 3 : firmware PLL that creates clocks from external clock not locked Status bit 2 : always logic '1' Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock If all these bits are not set then the operation of the firmware is unreliable FEE64 module aida02 failed FEE64 module aida06 failed FEE64 module aida09 failed FEE64 module aida10 failed FEE64 module aida13 failed Calibration test result: Passed 9, Failed 5 If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module White Rabbit error counter test result: Passed 14, Failed 0 Understand the status reports as follows:- Status bit 3 : White Rabbit decoder detected an error in the received data Status bit 2 : Firmware registered WR error, no reload of Timestamp Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR FPGA Timestamp error counter test result: Passed 14, Failed 0 If any of these counts are reported as in error The ASIC readout system has detected a timeslip. That is the timestamp read from the time FIFO is not younger than the last
Attachment 1: Rates_2022-05-14_22-32-44.png

Attachment 2: Temp_2022-05-14_22-31-37.png

Attachment 3: Leakg_2022-05-14_22-30-28.png

500	Sat Jun 25 17:06:42 2022	BA, AA	Saturday 25 June 2022 16:00-00:00
Took over the night shift from Magda 18:00 : attachments 1-3 20:00 : attachments 4-6 22:00 : attachments 7-9 00:00 : attachments 10-12
Attachment 1: Stat_17.png

Attachment 2: leak_17.png

Attachment 3: Temp17.png

Attachment 4: Temp_20.png

Attachment 5: Stat_20.png

Attachment 6: lek_20.png

Attachment 7: stat_22.png

Attachment 8: temp_22.png

Attachment 9: lak_22.png

492	Wed Jun 22 23:18:45 2022	AM, OH, TD, MA	Thursday 23 June
00:00 TD Noticed on the last stats uploaded that AIDA08 had stopped sending signals. Attempted to recover restarting merger but this caused 01 to drop out. 00:10 DAQ recovered and AIDA01 recovered with a reboot 01:00 Attachments 1-4, white rabbit failures on aida07 and aida08, otherwise all good 03:00 Attachments 5-9, aida07 and aida08 failures on white rabbit and fpga timestamp, otherwise all good 05:00 Attachments 10-14, aida07 and aida08 failures on white rabbit and fpga timestamp continue, otherwise all good 07:00 Attachments 15-19, aida07 and aida08 failures on white rabbit and fpga timestamp continue, otherwise all good
Attachment 1: 220623_0100_whiterabbit.png

Attachment 2: 220623_0100_temps.png

Attachment 3: 220623_0100_stats.png

Attachment 4: 220623_0100_bias.png

Attachment 5: 220623_0300_whiterabbit.png

Attachment 6: 220623_0300_fpgatime.png

Attachment 7: 220623_0300_temps.png

Attachment 8: 220623_0300_stats.png

Attachment 9: 220623_0300_bias.png

Attachment 10: 220623_0500_fpgatime.png

Attachment 11: 220623_0500_whiterabbit.png

Attachment 12: 220623_0500_temps.png

Attachment 13: 220623_0500_stats.png

Attachment 14: 220623_0500_bias.png

Attachment 15: 220623_0700_fpgatime.png

Attachment 16: 220623_0700_whiterabbit.png

Attachment 17: 220623_0700_temps.png

Attachment 18: 220623_0700_stats.png

Attachment 19: 220623_0700_bias.png

463	Mon May 16 23:02:54 2022	AM	Tuesday 17th May 00:00-08:00
01:00: Attachments 1-3, System checks good 03:00: Attachments 4-6, System checks good 05:00: Attachments 7-9, System checks good 07:00: Attachments 10-12, System checks good
Attachment 1: 220512_0604_biasLeakage.png

Attachment 2: 220512_0603_temps.png

Attachment 3: 220512_0601_stats.png

Attachment 4: 220517_0300_temps.png

Attachment 5: 220517_0300_stats.png

Attachment 6: 220517_0300_biasLeakage.png

Attachment 7: 220517_0500_temps.png

Attachment 8: 220517_0500_stats.png

Attachment 9: 220517_0500_biasLeakage.png

Attachment 10: 220517_0700_temps.png

Attachment 11: 220517_0700_stats.png

Attachment 12: 220517_0700_biasLeakage.png

495	Fri Jun 24 00:34:55 2022	AM	Friday 24 June 00:00-08:00
01:30 Attachments 1-5, white rabbit and fpga timestamp failures, otherwise all good 03:30 Attachments 11-15, white rabbit and fpga timestamp failures, otherwise all good 05:30 Attachments 6-10, white rabbit and fpga timestamp failures, otherwise all good 07:30 Attachments 16-20, white rabbit and fpga timestamp failures, otherwise all good
Attachment 1: 220624_0130_fpgatime.png

Attachment 2: 220624_0130_whiterabbit.png

Attachment 3: 220624_0130_temps.png

Attachment 4: 220624_0130_stats.png

Attachment 5: 220624_0130_bias.png

Attachment 6: 220624_0530_fpgatime.png

Attachment 7: 220624_0530_whiterabbit.png

Attachment 8: 220624_0530_temps.png

Attachment 9: 220624_0530_stats.png

Attachment 10: 220624_0530_bias.png

Attachment 11: 220624_0330_fpgatime.png

Attachment 12: 220624_0330_whiterabbit.png

Attachment 13: 220624_0330_temps.png

Attachment 14: 220624_0330_stats.png

Attachment 15: 220624_0330_bias.png

Attachment 16: 220624_0730_fpga.png

Attachment 17: 220624_0730_whiterabbit.png

Attachment 18: 220624_0730_temps.png

Attachment 19: 220624_0730_stats.png

Attachment 20: 220624_0730_bias.png

676	Sat Dec 14 11:52:42 2024	TD	Saturday 14 December
11:00 Visual inspection FEE64 adaptor PCBs & cabling aida02 ground from/to other FEE64s disconnected - re-connected aida01, aida09, aida12 - ground cabling screws to Lemo 00.250 housings loose - tightemed 12:50 Cooling water pressure & temperature OK - attachments 1 2 12:59 relay #1 power ON 13:01 relay #2 power ON 13:07 aida06 starts - panic during startup, automatic restart following 3 minute timeout DAQ reset, setup Check ASIC Control - browser tab timeout AIDA MIDAS HTTPD server console log - attachment 3 Appears to have restored ASIC settings 2024Dec13-17.02.45 saved yesterday aida10 ASICs #1 & #2 positive input, ASICs #3 & #4 negative input slow comparator 0xa (all p+n junction FEE64s and aida10), 0xf (n+n Ohmic FEE64s) 13:28 tar ASIC settings - attachment 4 [npg@aidas-gsi]$ cd /MIDAS/FEE_ASIC [npg@aidas-gsi FEE_ASIC]$ tar cvf /tmp/FEE_ASIC.tar . System wide checks Sync ASIC clocks - attachment 5 Clock, ADC calibration, WR decoder, FPGA timestamp, PLL checks - attachments 6-11 all OK except aida02 WR decoder error WR timestamps OK - attachment 12 FEE64 temps OK - attachment 13 13:45 Detector bias ON - attachment 14 BNC PB-5 pulser settings - attachment 15 Pulser connected to all p+n junction FEE64s except aida10 ADC, DISC, PAUSE and MBS correlation scaler stats - attachments 16-19 aida02 rate significantly lower than yesterday - https://elog.gsi.de/despec/Implantation+Stack/8 high rates observed for aida08, aida11 and aida14 - which are not connected to a DSSSD! per FEE64 Rate spectra - attachment 20 per p+n junction FEE64 1.8.L spectra - attachment 21 aida09 pulser peak width 56 ch FWHM = 39 keV FWHM consistent electronic noise for all p+n junction FEE64s (cabling+DSSSD) electronic noise of p+n junction FEE64s (cabling only) higher and more variable cf. https://elog.gsi.de/despec/Implantation+Stack/8 attachment 5 per p+n junction FEE64 1.8.W spectra 20us FSR - attachments 22-23 per n+n Ohmic FEE64 1.8.W spectra 20us FSR - attachment 24 WR timestamps OK - attachment 25 14:43 DAQ STOP Data transfer enabled Select Tape Server -> Next Run DAQ GO data file R3 Merger, Tape Server - attachments 26-27 data transfer rate c. 900k data items/s cf c. 300k data items/s yesterday https://elog.gsi.de/despec/Implantation+Stack/8 16:45 DAQ STOP Data transfer disabled Detector bias OFF FEE64 power OFF
Attachment 1: 20241214_125048.jpg

Attachment 2: 20241214_125104.jpg

Attachment 3: asic_check.log
executing do_PreReset ::MASTERTS namespace already exists done executing do_PreReset executing do_PostSetup done executing do_PostSetup ASIC.tcl :- CheckASIC fetched file /MIDAS/FEE_ASIC => aida01 checking asic 1 Loaded ASIC 1 at 0x0000401c for FEE aida01 Second load re-activated at 0x0000401c for FEE aida01 Shifting out finished at 0 counts Read the control register from FEE aida01 ASIC 1 checking asic 2 Loaded ASIC 2 at 0x0000405c for FEE aida01 Second load re-activated at 0x0000405c for FEE aida01 Shifting out finished at 0 counts Read the control register from FEE aida01 ASIC 2 checking asic 3 Loaded ASIC 3 at 0x0000409c for FEE aida01 Second load re-activated at 0x0000409c for FEE aida01 Shifting out finished at 0 counts Read the control register from FEE aida01 ASIC 3 checking asic 4 Loaded ASIC 4 at 0x000040dc for FEE aida01 Second load re-activated at 0x000040dc for FEE aida01 Shifting out finished at 0 counts Read the control register from FEE aida01 ASIC 4 ASIC.tcl :- CheckASIC fetched file /MIDAS/FEE_ASIC => aida02 checking asic 1 Loaded ASIC 1 at 0x0000401c for FEE aida02 Second load re-activated at 0x0000401c for FEE aida02 Shifting out finished at 0 counts Read the control register from FEE aida02 ASIC 1 checking asic 2 Loaded ASIC 2 at 0x0000405c for FEE aida02 Second load re-activated at 0x0000405c for FEE aida02 Shifting out finished at 0 counts Read the control register from FEE aida02 ASIC 2 checking asic 3 Loaded ASIC 3 at 0x0000409c for FEE aida02 Second load re-activated at 0x0000409c for FEE aida02 Shifting out finished at 0 counts Read the control register from FEE aida02 ASIC 3 checking asic 4 Loaded ASIC 4 at 0x000040dc for FEE aida02 Second load re-activated at 0x000040dc for FEE aida02 Shifting out finished at 0 counts Read the control register from FEE aida02 ASIC 4 ASIC.tcl :- CheckASIC fetched file /MIDAS/FEE_ASIC => aida03 checking asic 1 Loaded ASIC 1 at 0x0000401c for FEE aida03 Second load re-activated at 0x0000401c for FEE aida03 Shifting out finished at 0 counts Read the control register from FEE aida03 ASIC 1 checking asic 2 Loaded ASIC 2 at 0x0000405c for FEE aida03 Second load re-activated at 0x0000405c for FEE aida03 Shifting out finished at 0 counts Read the control register from FEE aida03 ASIC 2 checking asic 3 Loaded ASIC 3 at 0x0000409c for FEE aida03 Second load re-activated at 0x0000409c for FEE aida03 Shifting out finished at 0 counts Read the control register from FEE aida03 ASIC 3 checking asic 4 Loaded ASIC 4 at 0x000040dc for FEE aida03 Second load re-activated at 0x000040dc for FEE aida03 Shifting out finished at 0 counts Read the control register from FEE aida03 ASIC 4 ASIC.tcl :- CheckASIC fetched file /MIDAS/FEE_ASIC => aida04 checking asic 1 Loaded ASIC 1 at 0x0000401c for FEE aida04 Second load re-activated at 0x0000401c for FEE aida04 Shifting out finished at 0 counts Read the control register from FEE aida04 ASIC 1 checking asic 2 Loaded ASIC 2 at 0x0000405c for FEE aida04 Second load re-activated at 0x0000405c for FEE aida04 Shifting out finished at 0 counts Read the control register from FEE aida04 ASIC 2 checking asic 3 Loaded ASIC 3 at 0x0000409c for FEE aida04 Second load re-activated at 0x0000409c for FEE aida04 Shifting out finished at 0 counts Read the control register from FEE aida04 ASIC 3 checking asic 4 Loaded ASIC 4 at 0x000040dc for FEE aida04 Second load re-activated at 0x000040dc for FEE aida04 Shifting out finished at 0 counts Read the control register from FEE aida04 ASIC 4 ASIC.tcl :- CheckASIC fetched file /MIDAS/FEE_ASIC => aida05 checking asic 1 Loaded ASIC 1 at 0x0000401c for FEE aida05 Second load re-activated at 0x0000401c for FEE aida05 Shifting out finished at 0 counts Read the control register from FEE aida05 ASIC 1 checking asic 2 Loaded ASIC 2 at 0x0000405c for FEE aida05 Second load re-activated at 0x0000405c for FEE aida05 Shifting out finished at 0 counts Read the control register from FEE aida05 ASIC 2 checking asic 3 Loaded ASIC 3 at 0x0000409c for FEE aida05 Second load re-activated at 0x0000409c for FEE aida05 Shifting out finished at 0 counts Read the control register from FEE aida05 ASIC 3 checking asic 4 Loaded ASIC 4 at 0x000040dc for FEE aida05 Second load re-activated at 0x000040dc for FEE aida05 Shifting out finished at 0 counts Read the control register from FEE aida05 ASIC 4 ASIC.tcl :- CheckASIC fetched file /MIDAS/FEE_ASIC => aida06 checking asic 1 Loaded ASIC 1 at 0x0000401c for FEE aida06 Second load re-activated at 0x0000401c for FEE aida06 Shifting out finished at 0 counts Read the control register from FEE aida06 ASIC 1 checking asic 2 Loaded ASIC 2 at 0x0000405c for FEE aida06 Second load re-activated at 0x0000405c for FEE aida06 Shifting out finished at 0 counts Read the control register from FEE aida06 ASIC 2 checking asic 3 Loaded ASIC 3 at 0x0000409c for FEE aida06 Second load re-activated at 0x0000409c for FEE aida06 Shifting out finished at 0 counts Read the control register from FEE aida06 ASIC 3 checking asic 4 Loaded ASIC 4 at 0x000040dc for FEE aida06 Second load re-activated at 0x000040dc for FEE aida06 Shifting out finished at 0 counts Read the control register from FEE aida06 ASIC 4 ASIC.tcl :- CheckASIC fetched file /MIDAS/FEE_ASIC => aida07 checking asic 1 Loaded ASIC 1 at 0x0000401c for FEE aida07 Second load re-activated at 0x0000401c for FEE aida07 Shifting out finished at 0 counts Read the control register from FEE aida07 ASIC 1 checking asic 2 Loaded ASIC 2 at 0x0000405c for FEE aida07 Second load re-activated at 0x0000405c for FEE aida07 Shifting out finished at 0 counts Read the control register from FEE aida07 ASIC 2 checking asic 3 Loaded ASIC 3 at 0x0000409c for FEE aida07 Second load re-activated at 0x0000409c for FEE aida07 Shifting out finished at 0 counts Read the control register from FEE aida07 ASIC 3 checking asic 4 Loaded ASIC 4 at 0x000040dc for FEE aida07 Second load re-activated at 0x000040dc for FEE aida07 Shifting out finished at 0 counts Read the control register from FEE aida07 ASIC 4 ASIC.tcl :- CheckASIC fetched file /MIDAS/FEE_ASIC => aida08 checking asic 1 Loaded ASIC 1 at 0x0000401c for FEE aida08 Second load re-activated at 0x0000401c for FEE aida08 Shifting out finished at 0 counts Read the control register from FEE aida08 ASIC 1 checking asic 2 Loaded ASIC 2 at 0x0000405c for FEE aida08 Second load re-activated at 0x0000405c for FEE aida08 Shifting out finished at 0 counts Read the control register from FEE aida08 ASIC 2 checking asic 3 Loaded ASIC 3 at 0x0000409c for FEE aida08 Second load re-activated at 0x0000409c for FEE aida08 Shifting out finished at 0 counts Read the control register from FEE aida08 ASIC 3 checking asic 4 Loaded ASIC 4 at 0x000040dc for FEE aida08 Second load re-activated at 0x000040dc for FEE aida08 Shifting out finished at 0 counts Read the control register from FEE aida08 ASIC 4 ASIC.tcl :- CheckASIC fetched file /MIDAS/FEE_ASIC => aida09 checking asic 1 Loaded ASIC 1 at 0x0000401c for FEE aida09 Second load re-activated at 0x0000401c for FEE aida09 Shifting out finished at 0 counts Read the control register from FEE aida09 ASIC 1 checking asic 2 Loaded ASIC 2 at 0x0000405c for FEE aida09 Second load re-activated at 0x0000405c for FEE aida09 Shifting out finished at 0 counts Read the control register from FEE aida09 ASIC 2 checking asic 3 Loaded ASIC 3 at 0x0000409c for FEE aida09 Second load re-activated at 0x0000409c for FEE aida09 Shifting out finished at 0 counts Read the control register from FEE aida09 ASIC 3 checking asic 4 Loaded ASIC 4 at 0x000040dc for FEE aida09 Second load re-activated at 0x000040dc for FEE aida09 Shifting out finished at 0 counts Read the control register from FEE aida09 ASIC 4 ASIC.tcl :- CheckASIC fetched file /MIDAS/FEE_ASIC => aida10 checking asic 1 Loaded ASIC 1 at 0x0000401c for FEE aida10 Second load re-activated at 0x0000401c for FEE aida10 Shifting out finished at 0 counts Read the control register from FEE aida10 ASIC 1 checking asic 2 Loaded ASIC 2 at 0x0000405c for FEE aida10 Second load re-activated at 0x0000405c for FEE aida10 Shifting out finished at 0 counts Read the control register from FEE aida10 ASIC 2 checking asic 3 Loaded ASIC 3 at 0x0000409c for FEE aida10 Second load re-activated at 0x0000409c for FEE aida10 Shifting out finished at 0 counts Read the control register from FEE aida10 ASIC 3 checking asic 4 Loaded ASIC 4 at 0x000040dc for FEE aida10 Second load re-activated at 0x000040dc for FEE aida10 Shifting out finished at 0 counts Read the control register from FEE aida10 ASIC 4 ASIC.tcl :- CheckASIC fetched file /MIDAS/FEE_ASIC => aida11 checking asic 1 Loaded ASIC 1 at 0x0000401c for FEE aida11 Second load re-activated at 0x0000401c for FEE aida11 Shifting out finished at 0 counts Read the control register from FEE aida11 ASIC 1 checking asic 2 Loaded ASIC 2 at 0x0000405c for FEE aida11 Second load re-activated at 0x0000405c for FEE aida11 Shifting out finished at 0 counts Read the control register from FEE aida11 ASIC 2 checking asic 3 Loaded ASIC 3 at 0x0000409c for FEE aida11 Second load re-activated at 0x0000409c for FEE aida11 Shifting out finished at 0 counts Read the control register from FEE aida11 ASIC 3 checking asic 4 Loaded ASIC 4 at 0x000040dc for FEE aida11 Second load re-activated at 0x000040dc for FEE aida11 Shifting out finished at 0 counts Read the control register from FEE aida11 ASIC 4 ASIC.tcl :- CheckASIC fetched file /MIDAS/FEE_ASIC => aida12 checking asic 1 Loaded ASIC 1 at 0x0000401c for FEE aida12 Second load re-activated at 0x0000401c for FEE aida12 Shifting out finished at 0 counts Read the control register from FEE aida12 ASIC 1 checking asic 2 Loaded ASIC 2 at 0x0000405c for FEE aida12 Second load re-activated at 0x0000405c for FEE aida12 Shifting out finished at 0 counts Read the control register from FEE aida12 ASIC 2 checking asic 3 Loaded ASIC 3 at 0x0000409c for FEE aida12 Second load re-activated at 0x0000409c for FEE aida12 Shifting out finished at 0 counts Read the control register from FEE aida12 ASIC 3 checking asic 4 Loaded ASIC 4 at 0x000040dc for FEE aida12 Second load re-activated at 0x000040dc for FEE aida12 Shifting out finished at 0 counts Read the control register from FEE aida12 ASIC 4 ASIC.tcl :- CheckASIC fetched file /MIDAS/FEE_ASIC => aida13 checking asic 1 Loaded ASIC 1 at 0x0000401c for FEE aida13 Second load re-activated at 0x0000401c for FEE aida13 Shifting out finished at 0 counts Read the control register from FEE aida13 ASIC 1 checking asic 2 Loaded ASIC 2 at 0x0000405c for FEE aida13 Second load re-activated at 0x0000405c for FEE aida13 Shifting out finished at 0 counts Read the control register from FEE aida13 ASIC 2 checking asic 3 Loaded ASIC 3 at 0x0000409c for FEE aida13 Second load re-activated at 0x0000409c for FEE aida13 Shifting out finished at 0 counts Read the control register from FEE aida13 ASIC 3 checking asic 4 Loaded ASIC 4 at 0x000040dc for FEE aida13 Second load re-activated at 0x000040dc for FEE aida13 Shifting out finished at 0 counts Read the control register from FEE aida13 ASIC 4 ASIC.tcl :- CheckASIC fetched file /MIDAS/FEE_ASIC => aida14 checking asic 1 Loaded ASIC 1 at 0x0000401c for FEE aida14 Second load re-activated at 0x0000401c for FEE aida14 Shifting out finished at 0 counts Read the control register from FEE aida14 ASIC 1 checking asic 2 Loaded ASIC 2 at 0x0000405c for FEE aida14 Second load re-activated at 0x0000405c for FEE aida14 Shifting out finished at 0 counts Read the control register from FEE aida14 ASIC 2 checking asic 3 Loaded ASIC 3 at 0x0000409c for FEE aida14 Second load re-activated at 0x0000409c for FEE aida14 Shifting out finished at 0 counts Read the control register from FEE aida14 ASIC 3 checking asic 4 Loaded ASIC 4 at 0x000040dc for FEE aida14 Second load re-activated at 0x000040dc for FEE aida14 Shifting out finished at 0 counts Read the control register from FEE aida14 ASIC 4 ASIC.tcl :- CheckASIC fetched file /MIDAS/FEE_ASIC => aida15 ... 379 more lines ...
Attachment 4: FEE_ASIC.tar
Attachment 5: Screenshot_from_2024-12-14_13-30-48.png

Attachment 6: Screenshot_from_2024-12-14_13-30-54.png

Attachment 7: Screenshot_from_2024-12-14_13-31-02.png

Attachment 8: Screenshot_from_2024-12-14_13-35-22.png

Attachment 9: Screenshot_from_2024-12-14_13-35-28.png

Attachment 10: Screenshot_from_2024-12-14_13-35-33.png

Attachment 11: Screenshot_from_2024-12-14_13-36-06.png

Attachment 12: Screenshot_from_2024-12-14_13-36-27.png

Attachment 13: Screenshot_from_2024-12-14_13-36-42.png

Attachment 14: Screenshot_from_2024-12-14_13-44-29.png

Attachment 15: Screenshot_from_2024-12-14_13-46-41.png

Attachment 16: Screenshot_from_2024-12-14_13-54-58.png

Attachment 17: Screenshot_from_2024-12-14_13-55-19.png

Attachment 18: Screenshot_from_2024-12-14_13-55-33.png

Attachment 19: Screenshot_from_2024-12-14_13-56-00.png

Attachment 20: Screenshot_from_2024-12-14_14-10-08.png

Attachment 21: Screenshot_from_2024-12-14_14-14-18.png

Attachment 22: Screenshot_from_2024-12-14_14-26-30.png

Attachment 23: Screenshot_from_2024-12-14_14-27-16.png

Attachment 24: Screenshot_from_2024-12-14_14-29-24.png

Attachment 25: Screenshot_from_2024-12-14_14-42-40.png

Attachment 26: Screenshot_from_2024-12-14_14-43-51.png

Attachment 27: Screenshot_from_2024-12-14_14-43-58.png

645	Sun Jun 9 16:38:30 2024	Norah , Muneerah, JB	16:0-00:00 9 June 2024
AIDA02 and AIDA06 gave zero attachment 1. After connecting with Tom to fix it, now it works. 17:00 DSSSD bias & leakage current - attachment 2 FEE64 temperatures OK - attachment 3 Statistics attachment 4 17:39 Most of AIDA0 gave zero. I followed the instructions that Tom gave me to fix it, and now they work. 23:19 Flange removed. Starting to take beam.
Attachment 1: Screenshot_from_2024-06-09_17-24-13.png

Attachment 2: Screenshot_from_2024-06-09_18-00-27.png

Attachment 3: Screenshot_from_2024-06-09_18-01-49.png

Attachment 4: Screenshot_from_2024-06-09_18-01-23.png

458	Sun May 15 23:00:08 2022	& TD	Monday 16 May 00:00-08:00
00.01 DAQ continues file S450/R4_1319 ADC control register 0xff all disc outputs disabled ASIC settings 2021Apr29-13-16-00 slow comparator aida02 & aida04 0x16, aida06 & aida08 0x23, aida12 0xd, all others 0xc BNC PB-5 settings amplitude 1.000V attenuation x1 tau_d 1ms frequency 2Hz polarity + Disk space OK - /media/SecondDrive [npg@aidas-gsi S450]$ df -h Filesystem Size Used Avail Use% Mounted on devtmpfs 7.8G 0 7.8G 0% /dev tmpfs 7.8G 389M 7.4G 5% /dev/shm tmpfs 7.8G 19M 7.7G 1% /run tmpfs 7.8G 0 7.8G 0% /sys/fs/cgroup /dev/mapper/centos-root 50G 16G 35G 31% / /dev/sda2 1014M 226M 789M 23% /boot /dev/sda1 200M 12M 189M 6% /boot/efi /dev/sde1 7.2T 4.1T 2.8T 61% /media/SecondDrive /dev/mapper/centos-home 407G 91G 316G 23% /home tmpfs 1.6G 52K 1.6G 1% /run/user/1000 /dev/sdd1 7.2T 6.5T 310G 96% /run/media/npg/ThirdDrive 00.03 all histograms zero'd system wide checks counter baseline 00.08 check ASIC control - all FEE64s all ASICs Attachments 1 & 2 - DSSSD bias & Leakage current - OK grafana DSSSD bias, leakage current & temp - OK Attachment 3 - FEE64 temps OK Attachments 4-9 - adc, pause, resume & correlation scaler data items, push, flush stats Attachments 10-16 - TapeServer, NewMerger, NewMerger stats Attachment 17 - ucesb 04.08 Attachment 18 - DSSSD bias & Leakage current - OK Attachment 19 - FEE64 temps OK Attachment 20 - adc data item stats Attachments 21 - ucesb system wide checks - all OK except aida09 clock fail status 6 06.36 Attachment 22 - DSSSD bias & Leakage current - OK Attachment 23 - FEE64 temps OK Attachment 24 - adc data item stats Attachments 25 - ucesb system wide checks - all OK except aida09 clock fail status 6
Attachment 1: Screenshot_from_2022-05-16_00-10-13.png

Attachment 2: Screenshot_from_2022-05-16_00-10-43.png

Attachment 3: Screenshot_from_2022-05-16_00-11-18.png

Attachment 4: Screenshot_from_2022-05-16_00-11-50.png

Attachment 5: Screenshot_from_2022-05-16_00-12-27.png

Attachment 6: Screenshot_from_2022-05-16_00-12-54.png

Attachment 7: Screenshot_from_2022-05-16_00-13-25.png

Attachment 8: Screenshot_from_2022-05-16_00-13-55.png

Attachment 9: Screenshot_from_2022-05-16_00-14-22.png

Attachment 10: Screenshot_from_2022-05-16_00-15-46.png

Attachment 11: Screenshot_from_2022-05-16_00-16-08.png

Attachment 12: Screenshot_from_2022-05-16_00-16-36.png

Attachment 13: Screenshot_from_2022-05-16_00-16-58.png

Attachment 14: Screenshot_from_2022-05-16_00-16-58.png

Attachment 15: Screenshot_from_2022-05-16_00-17-32.png

Attachment 16: Screenshot_from_2022-05-16_00-17-55.png

Attachment 17: Screenshot_from_2022-05-16_00-18-45.png

Attachment 18: Screenshot_from_2022-05-16_04-08-34.png

Attachment 19: Screenshot_from_2022-05-16_04-09-07.png

Attachment 20: Screenshot_from_2022-05-16_04-09-57.png

Attachment 21: Screenshot_from_2022-05-16_04-10-27.png

Attachment 22: Screenshot_from_2022-05-16_06-35-32.png

Attachment 23: Screenshot_from_2022-05-16_06-36-37.png

Attachment 24: Screenshot_from_2022-05-16_06-37-04.png

Attachment 25: Screenshot_from_2022-05-16_06-37-58.png

Goto page Previous 1, 2, 3 ... 33, 34, 35

ELOG V3.1.4-unknown