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ID |
Date |
Author |
Subject |
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254
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Tue Apr 20 19:00:00 2021 |
JS | Tuesday 20th 20:00-00:00 |
20:00
Taking over from Liam, all systems good.
20:30
DB No faults.
Stats good
ucesb ok
20:58
DB No faults.
Stats good
Temps good
ucesb ok
21:31
DB No faults.
Stats good
Temps good
ucesb ok
22:02
DB No faults.
Stats good elog:254/3
Temps good elog:254/4
ucesb ok elog:254/1
Current ok elog:254/2
ADC Calibration check:
FEE64 module aida06 failed
Calibration test result: Passed 11, Failed 1
22:06 ucesb - DAQ Error - Onsite team checking daq crash
Tape server icon stopped spinning
Stats Rates 0, Counter aida01 zeroed but others normal. elog:254/5
Called Tom. Tried resetting in midas, no luck. Full reboot of DAQ and midas required.
According to log at 22:07 aida01 reset
Data taking stopped at 22:04 file R45_193
22:50
After a full power cycle all appear to be up and running well. Starting full checks.
23:00
Clock status test result: Passed 12, Failed 0
Calibration test result: Passed 12, Failed 0
White Rabbit error counter test result: Passed 12, Failed 0
Check FPGA is having a page error
Returned 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k
4k
aida01 : 4 8 2 2 1 3 1 4 2 3 7 :
39792
aida02 : 13 9 2 4 2 3 2 3 2 3 7 :
39708
aida03 : 19 5 4 3 1 3 1 4 2 3 7 :
39892
aida04 : 14 5 2 2 0 5 2 3 2 3 7 :
39744
aida05 : 16 11 3 2 2 4 3 2 1 4 7 :
40584
aida06 : 15 9 5 2 2 2 1 4 2 3 7 :
39828
aida07 : 15 9 3 3 2 2 1 4 2 3 7 :
39828
aida08 : 21 4 3 4 2 2 1 4 2 3 7 :
39844
aida09 : 11 6 1 2 3 4 2 3 2 3 7 :
39788
aida10 : 0 6 4 2 0 3 2 3 2 3 7 :
39472
aida11 : 16 7 2 0 1 3 2 3 2 3 7 :
39512
aida12 : 3 7 4 1 3 2 2 3 2 3 7 :
39524
DB No faults.
Stats good elog:254/6
Temps good elog:254/7 aida01 had been high during reboot issue, >70, but now is back down
Current ok elog:254/8
ucesb ok
23:25
DB No faults.
Stats good
Temps good
ucesb ok
23:42 No Beam
23:48 Beam Back
23:57
DB No faults.
Stats good elog:254/11
Temps good elog:254/12
ucesb ok elog:254/9
Current ok elog:254/10
Clock status test result: Passed 12, Failed 0
Calibration test result: Passed 12, Failed 0
White Rabbit error counter test result: Passed 12, Failed 0
*FPGA check page error*
Returned 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 27 9 5 2 1 2 1 4 2 3 7 : 39812
aida02 : 13 9 5 2 2 2 1 4 2 3 7 : 39820
aida03 : 21 8 3 2 2 2 1 4 2 3 7 : 39812
aida04 : 13 4 3 1 1 5 2 3 2 3 7 : 39780
aida05 : 24 5 3 2 2 4 2 3 2 3 7 : 39800
aida06 : 16 5 5 2 2 2 1 4 2 3 7 : 39800
aida07 : 22 6 2 2 1 3 1 4 2 3 7 : 39848
aida08 : 21 8 2 3 2 2 1 4 2 3 7 : 39828
aida09 : 18 7 1 1 3 4 2 3 2 3 7 : 39792
aida10 : 19 3 3 1 0 3 2 3 2 3 7 : 39476
aida11 : 17 4 4 0 1 3 2 3 2 3 7 : 39524
aida12 : 13 4 3 2 3 1 2 3 2 3 7 : 39428
00:04 Handing over to Corrigan |
| Attachment 1: 40.png
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| Attachment 2: 41.png
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| Attachment 3: Screenshot_2021-04-20_Statistics_aidas-gsi(3).png
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.png.png "Screenshot_2021-04-20_Statistics_aidas-gsi(3).png")
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| Attachment 4: Screenshot_2021-04-20_Temperature_and_status_scan_aidas-gsi(3).png
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.png.png "Screenshot_2021-04-20_Temperature_and_status_scan_aidas-gsi(3).png")
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| Attachment 5: Screenshot_2021-04-20_Statistics_aidas-gsi(4).png
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.png.png "Screenshot_2021-04-20_Statistics_aidas-gsi(4).png")
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| Attachment 6: Screenshot_2021-04-20_Statistics_aidas-gsi(5).png
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.png.png "Screenshot_2021-04-20_Statistics_aidas-gsi(5).png")
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| Attachment 7: Screenshot_2021-04-20_Temperature_and_status_scan_aidas-gsi(4).png
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.png.png "Screenshot_2021-04-20_Temperature_and_status_scan_aidas-gsi(4).png")
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| Attachment 8: 42.png
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| Attachment 9: 44.png
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| Attachment 10: 45.png
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| Attachment 11: Screenshot_2021-04-20_Statistics_aidas-gsi(6).png
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.png.png "Screenshot_2021-04-20_Statistics_aidas-gsi(6).png")
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| Attachment 12: Screenshot_2021-04-20_Temperature_and_status_scan_aidas-gsi(5).png
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.png.png "Screenshot_2021-04-20_Temperature_and_status_scan_aidas-gsi(5).png")
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253
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Tue Apr 20 14:56:38 2021 |
LPG | Tuesday 20th 16:00-20:00 |
16:00
New shift, ready to go! Beam stopped just as I started... Waiting for update.
Beam back at 16:08, ucesb scalers shown in elog:253/1
Database ok!
Stats ok!
ucesb ok!
Temperatures ok! elog:253/2
Statistics ok! elog:253/3
Leakage currents ok! Steadily rising, day/night effect? - elog:253/4 and elog:253/5
16:21
Online histograms zeroed in MIDAS. Same done in MBS DAQ.
16:45
Database ok!
Stats ok!
ucesb ok!
System wide checks:
Clock ok!
ADC 1 failed:
FEE64 module aida06 failed
WR ok!
FPGA ok!
Memory ok!
17:15
Database ok!
Stats ok!
ucesb ok!
17:45
Database ok!
Stats ok!
ucesb ok!
18:15
Database ok!
Stats ok!
ucesb ok!
System wide checks:
Clock ok!
ADC 1 fail:
FEE64 module aida06 failed
Calibration test result: Passed 11, Failed 1
WR ok!
FPGA ok!
Memory ok!
MIDAS Rates ok! elog:253/6
Temperatures ok! elog:253/7
Leakage currents ok, but still slowly rising! Topped out at ~20:30 yesterday elog:253/8
18:42
Message in the Merger terminal window (elog:253/9)
MERGE Actor (15671): Working with 0 from 12 data sources
19:05
Database ok!
Stats ok!
ucesb ok!
19:30
Some MIDAS spectra in elog:253/10 and elog:253/11
Database ok!
Stats ok!
ucesb ok!
19:50
Database ok!
Stats ok!
ucesb ok! elog:253/12
System wide checks:
Clock ok!
ADC 1 fail:
FEE64 module aida06 failed
Calibration test result: Passed 11, Failed 1
WR ok!
FPGA ok!
Memory ok!
MIDAS Rates ok! elog:253/13
Temperatures ok! elog:253/14
Leakage currents ok, now plateaued! elog:253/15
19:55 - Handing over to James  |
| Attachment 1: Screenshot_2021-04-20_at_15.09.52.png
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| Attachment 2: Screenshot_2021-04-20_Temperature_and_status_scan_aidas-gsi.png
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| Attachment 3: Screenshot_2021-04-20_Statistics_aidas-gsi.png
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| Attachment 4: lpg1.png
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| Attachment 5: Screenshot_2021-04-20_at_15.13.14.png
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| Attachment 6: Screenshot_2021-04-20_Statistics_aidas-gsi.png
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| Attachment 7: Screenshot_2021-04-20_Temperature_and_status_scan_aidas-gsi(1).png
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.png.png "Screenshot_2021-04-20_Temperature_and_status_scan_aidas-gsi(1).png")
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| Attachment 8: lpg2.png
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| Attachment 9: lpg3_merger.png
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| Attachment 10: Screenshot_2021-04-20_Spectrum_Browser_aidas-gsi.png
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| Attachment 11: Screenshot_2021-04-20_Spectrum_Browser_aidas-gsi(1).png
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.png.png "Screenshot_2021-04-20_Spectrum_Browser_aidas-gsi(1).png")
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| Attachment 12: Screenshot_2021-04-20_at_18.50.56.png
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| Attachment 13: Screenshot_2021-04-20_Statistics_aidas-gsi(2).png
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.png.png "Screenshot_2021-04-20_Statistics_aidas-gsi(2).png")
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| Attachment 14: Screenshot_2021-04-20_Temperature_and_status_scan_aidas-gsi(2).png
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.png.png "Screenshot_2021-04-20_Temperature_and_status_scan_aidas-gsi(2).png")
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| Attachment 15: lpg3.png
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252
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Tue Apr 20 10:54:41 2021 |
CB | April 20 12:00 - 16:00 shift |
11:55 CA got AIDA back online
12:00 Stats OK (attach 1)
No faults found
UCESB OK - no beam atm (attach 2)
Temps OK (running hotter than yesterday, but not worrying yet) - attach 3
Bias OK (attach 4)
System wide checks
Clock - *all* pass
ADC - 06 fails
WR - *all* pass
FPGA *all* pass
Memory info
Returned 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 13 4 1 3 2 1 2 4 2 3 7 : 39876
aida02 : 23 6 1 2 2 2 1 4 2 3 7 : 39772
aida03 : 24 4 4 1 2 3 1 4 2 3 7 : 39904
aida04 : 10 3 1 1 1 3 1 4 2 3 7 : 39728
aida05 : 12 2 3 2 1 4 2 3 1 4 7 : 40688
aida06 : 10 5 4 2 2 3 3 4 2 3 7 : 40400
aida07 : 22 6 1 3 1 3 1 4 2 3 7 : 39864
aida08 : 20 4 4 1 2 3 2 4 2 3 7 : 40144
aida09 : 1 2 2 3 1 2 1 3 3 3 7 : 40148
aida10 : 3 3 1 2 2 2 2 3 2 3 7 : 39412
aida11 : 25 7 0 1 0 3 2 3 2 3 7 : 39484
aida12 : 21 7 3 1 3 2 2 3 2 3 7 : 39580
Waiting for beam.
12:42 Stats OK, UCESB ok, No faults. No beam.
13:21 Stats OK, UCESB ok, No faults. No beam.
13:24 Implants in DSSD#3. ASIC check. Disappeared. No beam.
14:00 No beam.
Stats OK (attach 5)
Temps OK (attach 6)
UCESB OK
Bias OK (attach 7)
System wide checks
Clock OK
ADC calibration 06 fails
WR OK
FPGA OK
Returned 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 16 9 4 1 3 2 3 3 2 3 7 : 39848
aida02 : 15 8 2 2 2 3 2 3 2 3 7 : 39644
aida03 : 8 1 2 3 4 3 2 3 2 3 7 : 39720
aida04 : 25 12 3 1 1 3 1 4 2 3 7 : 39892
aida05 : 13 4 4 4 0 3 2 3 1 4 7 : 40596
aida06 : 21 8 3 3 0 3 3 4 2 3 7 : 40356
aida07 : 17 11 0 1 1 3 1 4 2 3 7 : 39804
aida08 : 16 8 2 3 2 3 1 4 2 3 7 : 39936
aida09 : 17 6 3 2 1 2 1 4 2 3 7 : 39716
aida10 : 3 3 2 2 4 1 2 2 3 3 7 : 39940
aida11 : 4 4 4 1 1 3 3 2 2 3 7 : 39248
aida12 : 2 4 1 3 1 2 2 3 2 3 7 : 39384
14:30 Stats OK, UCESB ok, No faults. No beam.
15:00 Stats OK, UCESB ok, No faults. No beam.
15:24 Beam is back!
Stats OK (attach 8), UCESB ok (attach 9), No faults.
15:50 Shift handed over to Liam |
| Attachment 1: Stats1.png
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| Attachment 2: ucesb_nobeam.png
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| Attachment 3: Temps1.png
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| Attachment 4: Bias1.png
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| Attachment 5: Stats2.png
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| Attachment 6: Temps2.png
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| Attachment 7: Bias2.png
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| Attachment 8: Stats3.png
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| Attachment 9: UCESB2.png
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251
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Tue Apr 20 07:06:20 2021 |
CA | April 20th 08:00 - 12:00 |
08:09 DAQ crashes at start of shift (!)
again happens at same time as beam being lost
All FEE64 lost connection
Beam downtime for next 3-4 hours
Performed powercycle and reset
08:40 AIDA back up and running, writing to R36
08:42 *all* system wide checks ok
temperatures ok - attachment 1
statistics ok - attachment 2
detector bias/leakage currents ok - attachment 3
08:57 options file size check;
Collecting the file size of each FEE64 Options CONTENTS file to check they are all the same
FEE : aida01 => Options file size is 1025 Last changed Tue Apr 20 08:22:14 CEST 2021
FEE : aida02 => Options file size is 1014 Last changed Fri Apr 16 00:56:20 CEST 2021
FEE : aida03 => Options file size is 1014 Last changed Wed Apr 14 21:52:04 CEST 2021
FEE : aida04 => Options file size is 1025 Last changed Sat Apr 17 06:07:36 CEST 2021
FEE : aida05 => Options file size is 1025 Last changed Fri Apr 16 00:53:25 CEST 2021
FEE : aida06 => Options file size is 1014 Last changed Wed Apr 14 21:52:04 CEST 2021
FEE : aida07 => Options file size is 1014 Last changed Wed Apr 14 21:52:04 CEST 2021
FEE : aida08 => Options file size is 1014 Last changed Wed Apr 14 21:52:04 CEST 2021
FEE : aida09 => Options file size is 1014 Last changed Wed Apr 14 21:52:05 CEST 2021
FEE : aida10 => Options file size is 1014 Last changed Wed Apr 14 21:52:06 CEST 2021
FEE : aida11 => Options file size is 1014 Last changed Wed Apr 14 21:52:05 CEST 2021
FEE : aida12 => Options file size is 1025 Last changed Mon Apr 19 09:05:25 CEST 2021
08:59 no error messages in database check terminal
stats ok
09:16 waveforms - attachments 4 & 5
09:30 no error messages in database check terminal
stats ok
10:07 no error messages in database check terminal
stats ok
10:30 aida01, aida02, aida03, aida04, aida07 lost connection, DAQ crashes
powercycle attempted, but FEE modules remain unconnected
TD performs further power cycle
11.12 reboot aida05
DAQ reset/setup
system wide checks
sync asic clocks OK
clock status & fpga timestamp errors OK
WR decoder status
Base Current Difference
aida09 fault 0xb307 : 0xb307 : 0
aida09 : WR status 0x40
aida10 fault 0x3d6c : 0x3d6c : 0
aida10 : WR status 0x40
aida11 fault 0xa610 : 0xa610 : 0
aida11 : WR status 0x40
aida12 fault 0x7c7 : 0x7c7 : 0
aida12 : WR status 0x40
White Rabbit error counter test result: Passed 8, Failed 4
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
NH had access to area, unplugged and replugged HDMI cables from aida09, aida10, aida11, aida12 root to MACB (at both ends)
earlier on, Akash secured HDMI cable to aida07
11:55 AIDA powercycle and reset, DAQ ok now
writing to file NULL/R45
12:00 CB takes over |
| Attachment 1: Screenshot_from_2021-04-20_07-45-09.png
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| Attachment 2: Screenshot_from_2021-04-20_07-45-43.png
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| Attachment 3: Screenshot_from_2021-04-20_07-46-05.png
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| Attachment 4: Screenshot_from_2021-04-20_08-14-58.png
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| Attachment 5: Screenshot_from_2021-04-20_08-15-38.png
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250
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Mon Apr 19 23:01:02 2021 |
OH | 20th April 00:00-08:00 |
23:52 Noticed AIDA07 has dropped out of the merger and is producing no statistics
Powercycling to recover
00:14 All FEEs recovered from powercycle
aida09 running again at HEC threshold of 0x2 (Was set to 0x1 earlier in the day while testing the HEC event disparity in DSSD3)
Now writing to R34
Following the powercycle the rates in the FEEs are much improved and back to where they were before the 08:30 crash on the 19th. - Attachment 1
Waveforms also look improved - attachmens 2 and 3
Current system parameters
ASIC settings Dec19 (All LEC comparator 0xa)
Pulser at 2V and 2Hz
DSSD 1 and 2 Bias 160V
DSSD 3 at 120V (Will lower to 100 again during the beam off period tomorrow)
00:28 In analysis of R34_13 the number of HEC items in DSSD3 appears to make sense again. The number in aida09 are consistent with the number in aida05 and the same for aida11 and aida07.
This appears to confirm that the earlier HEC issues we were observing were hardware related but we are unsure what/why/how these issues were caused.
Analysis - attachment 4
00:40 Issue with one of the FRS magnets so they stop recording data. Leaving AIDA running.
01:08 While beam was down have reset DSSD3 bias to 100V as was agreed with Tom and Nic in email
Leakage current decreased as expected - attachment 5
Once beam is back will check HEC still as expected.
01:14 Last magnet in FRS has an issue with the water flowing. Either sensor issue or water flow is to low.
Hakke have increased the water flow to hopefully keep the water running.
Beam is back.
From ucesb it seems that the HEC events in DSSD3 are still appearing as expected. Will check a file once we have a complete file.
Checked R34_36 and the HEC events in DSSD3 are still consistent - attachment 6
2:20 Statistics ok - attachment 7
Temp - attachment 8
Bias and leakage current ok - attachment 9
All system wide checks ok except for WR error check:
Base Current Difference
aida07 fault 0x9154 : 0x915b : 7
aida10 fault 0x8d3 : 0x8d3 : 0
aida10 : WR status 0x10
White Rabbit error counter test result: Passed 10, Failed 2
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
Note aida07 reports two bad timestamps in the merger
MERGE Data Link (3762): bad timestamp 6 3 0xc1817ea7 0x04a8fc66 0x0000683974a8fc66 0x1677683974a8fc66 0x167768397a546a56
MERGE Data Link (3762): bad timestamp 6 3 0xc1b77e25 0x04a8fc66 0x0000683974a8fc66 0x1677683974a8fc66 0x167768397a546a56
02:25 Remembered during a pre-experiment meeting with Vic, Patrick and Carl they mentioned the merger would track timestamp sequence errors
Can confirm this is true. Can see the two in aida07 in the counter in the merger stats page - attachment 10
02:45 Now up to 7 timestamp errors on aida07 in the merger
02:49 Ran R34_45 through AIDASort - It reports a greater number of implant events are able to have a front back match performed
Ratio between aida07 and 09 is 0.71 -> Double what it was before
Energy response of the HEC channels in aida07 and aida09 looks equivalent (left group aida09 right group aida11) - attahchment 11
04:40 Statistics ok - attachment 12
Temperatures ok - attachment 13
Bias and leakage currents - attachment 14
Clock status, ADC calibration and memory infomration all ok
aida07 fails both WR and FPGA
Base Current Difference
aida07 fault 0x915b : 0x9161 : 6
aida10 fault 0x8d3 : 0x8d3 : 0
aida10 : WR status 0x10
White Rabbit error counter test result: Passed 10, Failed 2
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
Base Current Difference
aida07 fault 0x0 : 0x1 : 1
FPGA Timestamp error counter test result: Passed 11, Failed 1
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
TS errors in the merger still only at 7 with all in aida07
06:25 Statistics - attachment 15
Temps ok - attachment 16
Bias and leakage currents ok - attachment 17
System wide checks: clock status, adc calibration and memory information all ok
WR multiple fails
Base Current Difference
aida05 fault 0xc9ca : 0xc9cb : 1
aida06 fault 0xe900 : 0xe901 : 1
aida07 fault 0x915b : 0x9166 : 11
aida08 fault 0x641e : 0x641f : 1
aida10 fault 0x8d3 : 0x8d3 : 0
aida10 : WR status 0x10
White Rabbit error counter test result: Passed 7, Failed 5
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
FPGA aida07 fails with difference of 1
No new TS sequence errors in merger
07:10 Beam has dropped out.
07:14 Beam is back |
| Attachment 1: 210420_0016_Stats.png
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| Attachment 2: 210420_0021_Layout7.png
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| Attachment 3: 210420_0022_Layout8.png
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| Attachment 4: 210420_0026_R34_13_Analysis.txt
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*** TDR format 3.3.0 analyser - TD - January 2019
*** ERROR: READ I/O error: 5002
blocks: 32000
ADC data format: 255975543 ( 1356743.5 Hz)
Other data format: 5944457 ( 31507.3 Hz)
Sample trace data format: 0 ( 0.0 Hz)
Undefined format: 0 ( 0.0 Hz)
Other data format type: PAUSE: 0 ( 0.0 Hz)
RESUME: 0 ( 0.0 Hz)
SYNC100: 32703 ( 173.3 Hz)
WR48-63: 32703 ( 173.3 Hz)
FEE64 disc: 1073243 ( 5688.5 Hz)
MBS info: 4805808 ( 25472.2 Hz)
Other info: 0 ( 0.0 Hz)
ADC data range bit set: 345437 ( 1830.9 Hz)
Timewarps: ADC: 0 ( 0.0 Hz)
PAUSE: 0 ( 0.0 Hz)
RESUME: 0 ( 0.0 Hz)
SYNC100: 0 ( 0.0 Hz)
WR48-63: 0 ( 0.0 Hz)
FEE64 disc: 0 ( 0.0 Hz)
MBS info: 0 ( 0.0 Hz)
Undefined: 0 ( 0.0 Hz)
Sample trace: 0 ( 0.0 Hz)
*** Timestamp elapsed time: 188.669 s
FEE elapsed dead time(s) elapsed idle time(s)
1 0.000 46.534
2 0.000 63.789
3 0.000 54.847
4 0.000 174.519
5 0.000 123.945
6 0.000 113.898
7 0.000 135.923
8 0.000 59.774
9 0.000 27.296
10 0.000 12.263
11 0.000 65.598
12 0.000 0.000
13 0.000 0.000
14 0.000 0.000
15 0.000 0.000
16 0.000 0.000
17 0.000 0.000
18 0.000 0.000
19 0.000 0.000
20 0.000 0.000
21 0.000 0.000
22 0.000 0.000
23 0.000 0.000
24 0.000 0.000
25 0.000 0.000
26 0.000 0.000
27 0.000 0.000
28 0.000 0.000
29 0.000 0.000
30 0.000 0.000
31 0.000 0.000
32 0.000 0.000
*** Statistics
FEE ADC Data Other Data Sample Undefined Pause Resume SYNC100 WR48-63 Disc MBS Other HEC Data
0 14400003 100475 0 0 0 0 1767 1767 95813 1128 0 35602
1 23251868 63483 0 0 0 0 2988 2988 57507 0 0 21204
2 17192461 2025458 0 0 0 0 2415 2415 200396 1820232 0 34093
3 20019932 1908259 0 0 0 0 2815 2815 81941 1820688 0 32715
4 3059738 405674 0 0 0 0 403 403 100680 304188 0 35774
5 10595698 355900 0 0 0 0 1322 1322 58122 295134 0 21319
6 12037952 388178 0 0 0 0 1554 1554 105230 279840 0 34521
7 9390918 368608 0 0 0 0 1205 1205 81600 284598 0 31165
8 46854628 72459 0 0 0 0 5872 5872 60715 0 0 21758
9 43874737 60599 0 0 0 0 5426 5426 49747 0 0 17382
10 36184433 112868 0 0 0 0 4528 4528 103812 0 0 31745
11 19113175 82496 0 0 0 0 2408 2408 77680 0 0 28159
12 0 0 0 0 0 0 0 0 0 0 0 0
13 0 0 0 0 0 0 0 0 0 0 0 0
14 0 0 0 0 0 0 0 0 0 0 0 0
15 0 0 0 0 0 0 0 0 0 0 0 0
16 0 0 0 0 0 0 0 0 0 0 0 0
17 0 0 0 0 0 0 0 0 0 0 0 0
18 0 0 0 0 0 0 0 0 0 0 0 0
19 0 0 0 0 0 0 0 0 0 0 0 0
20 0 0 0 0 0 0 0 0 0 0 0 0
21 0 0 0 0 0 0 0 0 0 0 0 0
22 0 0 0 0 0 0 0 0 0 0 0 0
23 0 0 0 0 0 0 0 0 0 0 0 0
24 0 0 0 0 0 0 0 0 0 0 0 0
25 0 0 0 0 0 0 0 0 0 0 0 0
26 0 0 0 0 0 0 0 0 0 0 0 0
27 0 0 0 0 0 0 0 0 0 0 0 0
28 0 0 0 0 0 0 0 0 0 0 0 0
29 0 0 0 0 0 0 0 0 0 0 0 0
30 0 0 0 0 0 0 0 0 0 0 0 0
31 0 0 0 0 0 0 0 0 0 0 0 0
32 0 0 0 0 0 0 0 0 0 0 0 0
*** Timewarps
FEE ADC Pause Resume SYNC100 WR48-63 Disc MBS Undefined Samples
0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0
2 0 0 0 0 0 0 0 0 0
3 0 0 0 0 0 0 0 0 0
4 0 0 0 0 0 0 0 0 0
5 0 0 0 0 0 0 0 0 0
6 0 0 0 0 0 0 0 0 0
7 0 0 0 0 0 0 0 0 0
8 0 0 0 0 0 0 0 0 0
9 0 0 0 0 0 0 0 0 0
10 0 0 0 0 0 0 0 0 0
11 0 0 0 0 0 0 0 0 0
12 0 0 0 0 0 0 0 0 0
13 0 0 0 0 0 0 0 0 0
14 0 0 0 0 0 0 0 0 0
15 0 0 0 0 0 0 0 0 0
16 0 0 0 0 0 0 0 0 0
17 0 0 0 0 0 0 0 0 0
18 0 0 0 0 0 0 0 0 0
19 0 0 0 0 0 0 0 0 0
20 0 0 0 0 0 0 0 0 0
21 0 0 0 0 0 0 0 0 0
22 0 0 0 0 0 0 0 0 0
23 0 0 0 0 0 0 0 0 0
24 0 0 0 0 0 0 0 0 0
25 0 0 0 0 0 0 0 0 0
26 0 0 0 0 0 0 0 0 0
27 0 0 0 0 0 0 0 0 0
28 0 0 0 0 0 0 0 0 0
29 0 0 0 0 0 0 0 0 0
30 0 0 0 0 0 0 0 0 0
31 0 0 0 0 0 0 0 0 0
32 0 0 0 0 0 0 0 0 0
*** Program elapsed time: 1641.051s ( 19.500 blocks/s, 1.219 Mb/s)
|
| Attachment 5: 210420_0109_Bias.png
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| Attachment 6: 210420_0026_R34_36_Analysis.txt
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*** TDR format 3.3.0 analyser - TD - January 2019
*** ERROR: READ I/O error: 5002
blocks: 32000
ADC data format: 255999603 ( 1309621.8 Hz)
Other data format: 5920397 ( 30287.1 Hz)
Sample trace data format: 0 ( 0.0 Hz)
Undefined format: 0 ( 0.0 Hz)
Other data format type: PAUSE: 0 ( 0.0 Hz)
RESUME: 0 ( 0.0 Hz)
SYNC100: 32728 ( 167.4 Hz)
WR48-63: 32728 ( 167.4 Hz)
FEE64 disc: 1044504 ( 5343.4 Hz)
MBS info: 4810437 ( 24608.8 Hz)
Other info: 0 ( 0.0 Hz)
ADC data range bit set: 327887 ( 1677.4 Hz)
Timewarps: ADC: 0 ( 0.0 Hz)
PAUSE: 0 ( 0.0 Hz)
RESUME: 0 ( 0.0 Hz)
SYNC100: 0 ( 0.0 Hz)
WR48-63: 0 ( 0.0 Hz)
FEE64 disc: 0 ( 0.0 Hz)
MBS info: 0 ( 0.0 Hz)
Undefined: 0 ( 0.0 Hz)
Sample trace: 0 ( 0.0 Hz)
*** Timestamp elapsed time: 195.476 s
FEE elapsed dead time(s) elapsed idle time(s)
1 0.000 51.325
2 0.000 68.599
3 0.000 55.115
4 0.000 180.174
5 0.000 140.295
6 0.000 123.427
7 0.000 138.446
8 0.000 55.510
9 0.000 13.463
10 0.000 24.357
11 0.000 74.336
12 0.000 0.000
13 0.000 0.000
14 0.000 0.000
15 0.000 0.000
16 0.000 0.000
17 0.000 0.000
18 0.000 0.000
19 0.000 0.000
20 0.000 0.000
21 0.000 0.000
22 0.000 0.000
23 0.000 0.000
24 0.000 0.000
25 0.000 0.000
26 0.000 0.000
27 0.000 0.000
28 0.000 0.000
29 0.000 0.000
30 0.000 0.000
31 0.000 0.000
32 0.000 0.000
*** Statistics
FEE ADC Data Other Data Sample Undefined Pause Resume SYNC100 WR48-63 Disc MBS Other HEC Data
0 14611253 94841 0 0 0 0 1936 1936 89802 1167 0 33511
1 23423897 61346 0 0 0 0 3006 3006 55334 0 0 20222
2 17311487 2050104 0 0 0 0 2477 2477 195362 1849788 0 32021
3 20533060 1944396 0 0 0 0 2862 2862 77493 1861179 0 30741
4 2942569 381933 0 0 0 0 417 417 93930 287169 0 33667
5 9776355 338395 0 0 0 0 1239 1239 56110 279807 0 20096
6 11887130 369619 0 0 0 0 1555 1555 103862 262647 0 32503
7 9239609 348065 0 0 0 0 1200 1200 76985 268680 0 29470
8 49507336 72711 0 0 0 0 6129 6129 60453 0 0 21190
9 44170393 65100 0 0 0 0 5430 5430 54240 0 0 18016
10 32977762 112783 0 0 0 0 4022 4022 104739 0 0 30280
11 19618752 81104 0 0 0 0 2455 2455 76194 0 0 26170
12 0 0 0 0 0 0 0 0 0 0 0 0
13 0 0 0 0 0 0 0 0 0 0 0 0
14 0 0 0 0 0 0 0 0 0 0 0 0
15 0 0 0 0 0 0 0 0 0 0 0 0
16 0 0 0 0 0 0 0 0 0 0 0 0
17 0 0 0 0 0 0 0 0 0 0 0 0
18 0 0 0 0 0 0 0 0 0 0 0 0
19 0 0 0 0 0 0 0 0 0 0 0 0
20 0 0 0 0 0 0 0 0 0 0 0 0
21 0 0 0 0 0 0 0 0 0 0 0 0
22 0 0 0 0 0 0 0 0 0 0 0 0
23 0 0 0 0 0 0 0 0 0 0 0 0
24 0 0 0 0 0 0 0 0 0 0 0 0
25 0 0 0 0 0 0 0 0 0 0 0 0
26 0 0 0 0 0 0 0 0 0 0 0 0
27 0 0 0 0 0 0 0 0 0 0 0 0
28 0 0 0 0 0 0 0 0 0 0 0 0
29 0 0 0 0 0 0 0 0 0 0 0 0
30 0 0 0 0 0 0 0 0 0 0 0 0
31 0 0 0 0 0 0 0 0 0 0 0 0
32 0 0 0 0 0 0 0 0 0 0 0 0
*** Timewarps
FEE ADC Pause Resume SYNC100 WR48-63 Disc MBS Undefined Samples
0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0
2 0 0 0 0 0 0 0 0 0
3 0 0 0 0 0 0 0 0 0
4 0 0 0 0 0 0 0 0 0
5 0 0 0 0 0 0 0 0 0
6 0 0 0 0 0 0 0 0 0
7 0 0 0 0 0 0 0 0 0
8 0 0 0 0 0 0 0 0 0
9 0 0 0 0 0 0 0 0 0
10 0 0 0 0 0 0 0 0 0
11 0 0 0 0 0 0 0 0 0
12 0 0 0 0 0 0 0 0 0
13 0 0 0 0 0 0 0 0 0
14 0 0 0 0 0 0 0 0 0
15 0 0 0 0 0 0 0 0 0
16 0 0 0 0 0 0 0 0 0
17 0 0 0 0 0 0 0 0 0
18 0 0 0 0 0 0 0 0 0
19 0 0 0 0 0 0 0 0 0
20 0 0 0 0 0 0 0 0 0
21 0 0 0 0 0 0 0 0 0
22 0 0 0 0 0 0 0 0 0
23 0 0 0 0 0 0 0 0 0
24 0 0 0 0 0 0 0 0 0
25 0 0 0 0 0 0 0 0 0
26 0 0 0 0 0 0 0 0 0
27 0 0 0 0 0 0 0 0 0
28 0 0 0 0 0 0 0 0 0
29 0 0 0 0 0 0 0 0 0
30 0 0 0 0 0 0 0 0 0
31 0 0 0 0 0 0 0 0 0
32 0 0 0 0 0 0 0 0 0
*** Program elapsed time: 5995.524s ( 5.337 blocks/s, 0.334 Mb/s)
|
| Attachment 7: 210420_0220_Stats.png
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| Attachment 8: 210420_0229_Temp.png
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| Attachment 9: 210420_0220_Bias.png
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|
| Attachment 10: 210420_0225_MergerStats.png
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| Attachment 11: Capture.PNG
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| Attachment 12: 210420_0437_stats.png
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|
| Attachment 13: 210420_0538_Temp.png
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| Attachment 14: 210420_0439_Bias.png
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|
| Attachment 15: 210420_0624_stats.png
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| Attachment 16: 210420_0624_Temp.png
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| Attachment 17: 210420_0625_Bias.png
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249
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Mon Apr 19 19:19:18 2021 |
CB | Monday 19 April 20:00-24:00 shift |
20:19
Statistics OK (attach 1)
No faults found
Ucesb OK (attach 2)
Temps OK (attach 3)
Bias OK (attach 4)
System-wide checks - as per last check
aida09 fails clock (OK)
aida07 and 09 fail calibration (OK)
Base Current Difference
aida05 fault 0xdb9a : 0xdb9d : 3
aida06 fault 0xb74f : 0xb752 : 3
aida07 fault 0xd052 : 0xd05f : 13
aida08 fault 0xe4c1 : 0xe4c4 : 3
aida09 fault 0xaf4b : 0xaf4d : 2
White Rabbit error counter test result: Passed 7, Failed 5
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
Base Current Difference
aida12 fault 0x0 : 0x29 : 41
FPGA Timestamp error counter test result: Passed 11, Failed 1
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
Returned 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 0 3 2 2 2 5 2 3 2 3 6 : 35704
aida02 : 19 4 1 1 1 2 2 3 3 3 6 : 36316
aida03 : 12 9 2 1 2 2 2 3 3 3 6 : 36408
aida04 : 16 3 5 4 2 4 2 3 3 3 6 : 36776
aida05 : 41 10 10 3 3 3 3 3 3 3 6 : 37172
aida06 : 25 21 9 3 2 3 1 4 3 3 6 : 37116
aida07 : 10 7 1 2 1 3 2 2 3 3 6 : 35952
aida08 : 33 7 5 1 1 2 2 3 3 3 6 : 36460
aida09 : 12 7 4 2 2 2 2 2 2 4 6 : 36968
aida10 : 16 6 2 1 1 4 3 3 2 3 6 : 35824
aida11 : 2 0 1 2 2 2 2 4 2 3 6 : 35800
aida12 : 15 6 2 0 2 4 2 2 3 3 6 : 36108
20:48 Started compressing *old* runs on Screen 2, Workspace 5
nice -n10 gzip -v R[...]_*
21:00 Stats OK, UCESB OK, No faults
21:07 Go4 spectra erased by remote shifters.
21:15 Local shifters report correlations lost. Beam may be intermittently removed for checks.
21:30 Still no beam. DAQ issues locally. AIDA MBS link had to be restarted due to operator mistake.
21:37 Beam back. Stats OK, UCESB OK, No faults found.
System wide checks:
Clock - aida09 fails
All modules now fail ADC calibration
FEE64 module aida01 failed
FEE64 module aida02 failed
FEE64 module aida03 failed
FEE64 module aida04 failed
FEE64 module aida05 failed
FEE64 module aida06 failed
FEE64 module aida07 failed
FEE64 module aida08 failed
FEE64 module aida09 failed
FEE64 module aida10 failed
FEE64 module aida11 failed
FEE64 module aida12 failed
Calibration test result: Passed 0, Failed 12
Base Current Difference
aida05 fault 0xdb9a : 0xdb9d : 3
aida06 fault 0xb74f : 0xb752 : 3
aida07 fault 0xd052 : 0xd061 : 15
aida08 fault 0xe4c1 : 0xe4c4 : 3
aida09 fault 0xaf4b : 0xaf4d : 2
White Rabbit error counter test result: Passed 7, Failed 5
Base Current Difference
aida12 fault 0x0 : 0x36 : 54
FPGA Timestamp error counter test result: Passed 11, Failed 1
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
Returned 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 2 6 3 1 2 4 2 4 2 3 6 : 36104
aida02 : 2 3 0 2 2 4 2 2 3 3 6 : 36064
aida03 : 6 3 3 3 2 2 2 2 4 3 6 : 36928
aida04 : 15 5 8 4 3 3 2 3 3 3 6 : 36772
aida05 : 10 5 8 4 4 4 3 2 3 3 6 : 36688
aida06 : 14 17 10 3 3 3 1 4 3 3 6 : 37120
aida07 : 3 4 1 1 1 2 2 2 3 3 6 : 35740
aida08 : 12 5 7 2 2 4 1 2 3 3 6 : 35976
aida09 : 0 6 2 0 2 2 2 2 2 4 6 : 36816
aida10 : 4 2 5 2 1 4 2 4 2 3 6 : 36080
aida11 : 14 3 2 3 1 2 2 4 2 3 6 : 35856
aida12 : 1 2 0 2 1 4 1 3 3 3 6 : 36244
22:05 Stats OK (attach 5)
Temps OK (attach 6)
Bias OK (attach 7)
System wide checks as before - see above.
22:13 ADC calibration - Only 06,07 and 09 now fail
(TD re-calibrated remotely)
22:53 Beam off to allow access to S4 to reboot VME crate (akash).
22:58 Started compressing *old* runs on Screen 2, Workspace 5
nice -n10 gzip -v R[1-2][0-9]_* R[3][0-2]_*
aka everything *except* R33_*
23:11: Beam is back. Stats and UCESB as before.
23:24: Stats OK (attach 8)
Temps OK (attach 9)
Bias OK (attach 10)
UCESB OK (attach 11)
System-wide checks
Clock: 06 fails
Calibration: 06,07,09 fail
Base Current Difference
aida05 fault 0xdb9a : 0xdb9d : 3
aida06 fault 0xb74f : 0xb752 : 3
aida07 fault 0xd052 : 0xd066 : 20
aida08 fault 0xe4c1 : 0xe4c4 : 3
aida09 fault 0xaf4b : 0xaf4d : 2
White Rabbit error counter test result: Passed 7, Failed 5
Base Current Difference
aida05 fault 0xdb9a : 0xdb9d : 3
aida06 fault 0xb74f : 0xb752 : 3
aida07 fault 0xd052 : 0xd066 : 20
aida08 fault 0xe4c1 : 0xe4c4 : 3
aida09 fault 0xaf4b : 0xaf4d : 2
White Rabbit error counter test result: Passed 7, Failed 5
Returned 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 15 8 2 2 3 4 3 3 2 3 6 : 35996
aida02 : 8 12 4 1 2 4 3 2 3 3 6 : 36448
aida03 : 2 4 2 4 3 3 1 3 3 3 6 : 36360
aida04 : 7 8 4 4 2 4 3 3 3 3 6 : 37020
aida05 : 3 5 7 4 3 3 3 3 3 3 6 : 36964
aida06 : 2 6 8 2 3 4 2 3 3 3 6 : 36792
aida07 : 8 4 5 2 0 3 1 2 3 4 6 : 37712
aida08 : 26 11 3 1 1 3 1 3 3 3 6 : 36304
aida09 : 22 4 2 2 3 4 1 3 3 3 6 : 36504
aida10 : 21 6 6 2 0 4 2 3 3 3 6 : 36644
aida11 : 22 7 2 3 2 1 2 4 2 3 6 : 35856
aida12 : 16 9 2 2 3 3 2 2 3 3 6 : 36136 |
| Attachment 1: Stats1.png
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| Attachment 2: Ucesb1.png
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| Attachment 3: Temps1.png
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| Attachment 4: Bias1.png
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| Attachment 5: Stats2.png
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| Attachment 6: Temp2.png
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| Attachment 7: Bias2.png
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| Attachment 8: Stats3.png
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| Attachment 9: Temps3.png
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| Attachment 10: Bias3.png
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| Attachment 11: Ucesb2.png
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248
|
Mon Apr 19 16:58:29 2021 |
LJW | Monday 19th April 16:00-20:00 Shift |
System Checks @ ~18:10 :
FEE64 module aida09 global clocks failed, 6
Clock status test result: Passed 11, Failed 1
Understand status as follows
Status bit 3 : firmware PLL that creates clocks from external clock not locked
Status bit 2 : always logic '1'
Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock
Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock
If all these bits are not set then the operation of the firmware is unreliable
FEE64 module aida07 failed
FEE64 module aida09 failed
Calibration test result: Passed 10, Failed 2
If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module
Base Current Difference
aida07 fault 0xd052 : 0xd05a : 8
White Rabbit error counter test result: Passed 11, Failed 1
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
Base Current Difference
aida12 fault 0x0 : 0x23 : 35
FPGA Timestamp error counter test result: Passed 11, Failed 1
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
Returned 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 1 6 4 0 1 5 2 3 2 3 6 : 35636
aida02 : 27 3 2 0 2 3 2 3 3 3 6 : 36516
aida03 : 33 9 2 1 1 3 2 3 3 3 6 : 36556
aida04 : 11 6 5 4 2 4 3 3 3 3 6 : 37036
aida05 : 15 8 7 4 3 4 4 2 3 3 6 : 36908
aida06 : 13 9 7 3 3 4 2 3 3 3 6 : 36876
aida07 : 1 3 3 2 2 3 1 3 3 3 6 : 36236
aida08 : 29 5 2 1 1 2 2 3 3 3 6 : 36380
aida09 : 3 8 2 0 2 3 2 2 2 4 6 : 36972
aida10 : 9 5 3 3 1 4 2 4 2 3 6 : 36124
aida11 : 5 7 3 2 2 2 2 4 2 3 6 : 35900
aida12 : 24 6 3 1 2 3 2 2 3 3 6 : 36064
System Checks @ ~19:55
FEE64 module aida09 global clocks failed, 6
Clock status test result: Passed 11, Failed 1
Understand status as follows
Status bit 3 : firmware PLL that creates clocks from external clock not locked
Status bit 2 : always logic '1'
Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock
Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock
If all these bits are not set then the operation of the firmware is unreliable
FEE64 module aida07 failed
FEE64 module aida09 failed
Calibration test result: Passed 10, Failed 2
If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module
Base Current Difference
aida05 fault 0xdb9a : 0xdb9d : 3
aida06 fault 0xb74f : 0xb752 : 3
aida07 fault 0xd052 : 0xd05e : 12
aida08 fault 0xe4c1 : 0xe4c4 : 3
aida09 fault 0xaf4b : 0xaf4d : 2
White Rabbit error counter test result: Passed 7, Failed 5
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
Base Current Difference
aida12 fault 0x0 : 0x27 : 39
FPGA Timestamp error counter test result: Passed 11, Failed 1
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
Returned 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 18 10 2 2 1 5 2 3 2 3 6 : 35768
aida02 : 21 9 2 1 2 2 2 3 3 3 6 : 36444
aida03 : 13 5 6 1 2 2 2 3 3 3 6 : 36444
aida04 : 30 11 4 3 2 4 3 3 3 3 6 : 37104
aida05 : 10 9 8 4 4 4 4 2 3 3 6 : 36976
aida06 : 22 17 10 3 2 3 1 4 3 3 6 : 37088
aida07 : 20 8 4 1 2 4 1 2 3 3 6 : 35952
aida08 : 14 4 3 0 1 2 2 3 3 3 6 : 36296
aida09 : 24 8 4 0 1 3 3 3 3 3 6 : 36768
aida10 : 19 8 4 1 1 4 2 3 3 3 6 : 36652
aida11 : 6 6 1 2 3 1 2 4 2 3 6 : 35800
aida12 : 15 7 1 1 2 4 1 2 3 3 6 : 35876 |
| Attachment 1: 63.png
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| Attachment 2: Screenshot_2021-04-19_Statistics_aidas-gsi(3).png
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.png.png "Screenshot_2021-04-19_Statistics_aidas-gsi(3).png")
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| Attachment 3: Screenshot_2021-04-19_Temperature_and_status_scan_aidas-gsi(4).png
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.png.png "Screenshot_2021-04-19_Temperature_and_status_scan_aidas-gsi(4).png")
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| Attachment 4: 64.png
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| Attachment 5: 65.png
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| Attachment 6: 66.png
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246
|
Mon Apr 19 13:27:08 2021 |
RDP | Monday 19th April 12 noon shift |
12.30 There appear to be fewer HEC events in aida09 cf. aida11 and upstream DSSSDs
Decrease aida09 asic #1-4 HEC fast comparator 0x2 -> 0x1
Online/nearline analyses of daat files indicates that this does not resolve the issue
Some timestamp issues
MERGE Data Link (23725): bad timestamp 11 3 0x8b620008 0x0287be94 0x00003dd78287be94 0x16773dd78287be94 0x16773dd78287beb2
MERGE Data Link (23725): bad timestamp 11 3 0x8b610040 0x073302ce 0x00003df3e73302ce 0x16773df3e73302ce 0x16773df3e73302ec
MERGE Data Link (23725): bad timestamp 11 3 0x8b610020 0x0a54b794 0x00003e4e4a54b794 0x16773e4e4a54b794 0x16773e4e4a54b7b2
MERGE Data Link (23725): bad timestamp 11 3 0x8b610020 0x052da21e 0x00003f68f52da21e 0x16773f68f52da21e 0x16773f68f52da232
MERGE Data Link (23725): bad timestamp 11 3 0x8b620008 0x0061489e 0x000040aa8061489e 0x167740aa8061489e 0x167740aa806148a8
MERGE Data Link (23725): bad timestamp 11 3 0x8b610008 0x04029d5e 0x00004169c4029d5e 0x16774169c4029d5e 0x16774169c4029d68
MERGE Data Link (23725): bad timestamp 11 3 0x8b630004 0x08dfcb14 0x0000417fd8dfcb14 0x1677417fd8dfcb14 0x1677417fd8dfcb28
MERGE Data Link (23725): bad timestamp 11 3 0x8b630020 0x08dfcb1e 0x0000417fd8dfcb1e 0x1677417fd8dfcb1e 0x1677417fd8dfcb28
13.50 Increased DSSSD# 3 bias from -100V
-100V -6.325uA
-110V -6.500uA
-120V -6.800uA
|
| Attachment 1: 61.png
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| Attachment 2: Screenshot_2021-04-19_Temperature_and_status_scan_aidas-gsi(2).png
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.png.png "Screenshot_2021-04-19_Temperature_and_status_scan_aidas-gsi(2).png")
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| Attachment 3: Screenshot_2021-04-19_Statistics_aidas-gsi(2).png
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.png.png "Screenshot_2021-04-19_Statistics_aidas-gsi(2).png")
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244
|
Mon Apr 19 06:46:15 2021 |
MS | Monday 19 April 07:47-12:00 2021 |
07:47
Clock status test result: Passed 12, Failed 0
Understand status as follows
Status bit 3 : firmware PLL that creates clocks from external clock not locked
Status bit 2 : always logic '1'
Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock
Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock
If all these bits are not set then the operation of the firmware is unreliable
FEE64 module aida06 failed
FEE64 module aida07 failed
FEE64 module aida10 failed
Calibration test result: Passed 9, Failed 3
If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module
Base Current Difference
aida01 fault 0x7686 : 0x768a : 4
aida02 fault 0x941d : 0x9421 : 4
aida03 fault 0x7cd7 : 0x7cdb : 4
aida04 fault 0xb86d : 0xb871 : 4
aida05 fault 0x1a59 : 0x1a61 : 8
aida06 fault 0x4f45 : 0x4f4d : 8
aida07 fault 0x3bfc : 0x3c46 : 74
aida08 fault 0xc7ce : 0xc7d5 : 7
aida09 fault 0xb33b : 0xb33c : 1
White Rabbit error counter test result: Passed 3, Failed 9
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
Base Current Difference
aida09 fault 0x1 : 0x2 : 1
aida12 fault 0xa : 0x35 : 43
FPGA Timestamp error counter test result: Passed 10, Failed 2
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
Returned 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 19 18 10 7 1 3 2 4 2 3 6 : 36380
aida02 : 11 15 5 3 2 3 2 3 1 4 6 : 36692
aida03 : 15 11 13 3 4 3 3 3 2 3 6 : 36164
aida04 : 22 14 20 5 1 3 4 3 2 3 6 : 36456
aida05 : 7 7 5 2 1 2 3 4 2 3 6 : 36132
aida06 : 21 14 6 2 3 3 1 2 2 4 6 : 37028
aida07 : 11 8 7 4 2 3 2 2 4 3 6 : 37212
aida08 : 18 10 7 5 3 1 4 3 2 3 6 : 36072
aida09 : 24 23 18 3 2 3 2 4 2 3 6 : 36504
aida10 : 6 19 5 2 2 2 2 3 2 3 6 : 35520
aida11 : 22 15 7 2 1 3 2 3 2 3 6 : 35648
aida12 : 35 13 8 2 5 3 1 3 3 3 6 : 36724
At 8:30 DAQ and Temperature Scan stopped working properly.
11:00
It was noted that at the time that AIDA dropped out ~8:30 the beam also dropped out. It seems a bit of a coincidence
TD and MS powercycled the FEEs after the first crash and restarted MIDAS but not the merger. This recovered the FEEs but did not re-establish the links between the FEEs and the Merger.
Another powercycle was performed this time with a full reset of the merger and the links were restored. Upon restoring there was a large amount of noise in across all FEEs on average a 50% increase across all FEEs but in DSSD a factor of 4-6 increase was common.
In the waveforms large 100kHz transiets could be seen - attachment 4
A further power-cycle was performed by OH. The rates following this powercycle are better than just before the power cycle but have not recovered to pre-glitch levels.
The waveforms here are much improved though - attachment 5 and 6
11:45
FEE64 module aida09 global clocks failed, 6
Clock status test result: Passed 11, Failed 1
Understand status as follows
Status bit 3 : firmware PLL that creates clocks from external clock not locked
Status bit 2 : always logic '1'
Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock
Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock
If all these bits are not set then the operation of the firmware is unreliable
FEE64 module aida01 failed
FEE64 module aida02 failed
FEE64 module aida03 failed
FEE64 module aida04 failed
FEE64 module aida05 failed
FEE64 module aida06 failed
FEE64 module aida07 failed
FEE64 module aida08 failed
FEE64 module aida09 failed
FEE64 module aida10 failed
FEE64 module aida11 failed
FEE64 module aida12 failed
Calibration test result: Passed 0, Failed 12
If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module
White Rabbit error counter test result: Passed 12, Failed 0
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
FPGA Timestamp error counter test result: Passed 12, Failed 0
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
Returned 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 1 2 2 1 2 4 2 4 2 3 7 : 40148
aida02 : 5 4 2 2 1 2 2 3 2 3 7 : 39380
aida03 : 3 2 1 1 1 3 1 4 2 3 7 : 39692
aida04 : 4 2 1 0 1 3 3 3 2 3 7 : 39664
aida05 : 2 7 2 0 2 2 3 4 2 3 7 : 40160
aida06 : 2 3 2 2 2 2 1 3 3 3 7 : 40192
aida07 : 23 7 2 0 0 3 2 4 2 3 7 : 39988
aida08 : 23 11 4 0 1 3 1 4 2 3 7 : 39860
aida09 : 1 3 1 1 2 4 1 3 1 4 7 : 40396
aida10 : 1 3 3 1 1 4 1 2 3 3 7 : 39852
aida11 : 3 0 2 3 1 2 3 2 2 3 7 : 39116
aida12 : 5 8 0 3 1 4 2 3 2 3 7 : 39668
|
| Attachment 1: Screenshot_2021-04-19_Statistics_aidas-gsi.png
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|
| Attachment 2: Screenshot_2021-04-19_Temperature_and_status_scan_aidas-gsi.png
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|
| Attachment 3: 42.png
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|
| Attachment 4: Screenshot_2021-04-19_Spectrum_Browser_aidas-gsi(1).png
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.png.png "Screenshot_2021-04-19_Spectrum_Browser_aidas-gsi(1).png")
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| Attachment 5: 210319_1054_Layout7.png
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| Attachment 6: 210419_1054_Layout8.png
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| Attachment 7: Screenshot_2021-04-19_Statistics_aidas-gsi(1).png
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.png.png "Screenshot_2021-04-19_Statistics_aidas-gsi(1).png")
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| Attachment 8: Screenshot_2021-04-19_Temperature_and_status_scan_aidas-gsi(1).png
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.png.png "Screenshot_2021-04-19_Temperature_and_status_scan_aidas-gsi(1).png")
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| Attachment 9: 43.png
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|
|
243
|
Mon Apr 19 01:08:40 2021 |
MA | Monday 19th April 00:00-08:00 |
03:09 General check
Rates, temptature, voltages are OK attached 1, 2, 3, 4
****Clock Ckeck******
OK
Clock status test result: Passed 12, Failed 0
Understand status as follows
Status bit 3 : firmware PLL that creates clocks from external clock not locked
Status bit 2 : always logic '1'
Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock
Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock
If all these bits are not set then the operation of the firmware is unreliable
******ADC check ******
FEE64 module aida06 failed
FEE64 module aida07 failed
FEE64 module aida10 failed
Calibration test result: Passed 9, Failed 3
If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module
****** White Rabbit check******
Base Current Difference
aida01 fault 0x7686 : 0x768a : 4
aida02 fault 0x941d : 0x9421 : 4
aida03 fault 0x7cd7 : 0x7cdb : 4
aida04 fault 0xb86d : 0xb871 : 4
aida05 fault 0x1a59 : 0x1a61 : 8
aida06 fault 0x4f45 : 0x4f4d : 8
aida07 fault 0x3bfc : 0x3c2c : 48
aida08 fault 0xc7ce : 0xc7d5 : 7
aida09 fault 0xb33b : 0xb33c : 1
White Rabbit error counter test result: Passed 3, Failed 9
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
*****FPGA check ******
Base Current Difference
aida09 fault 0x1 : 0x2 : 1
aida12 fault 0xa : 0x10 : 6
FPGA Timestamp error counter test result: Passed 10, Failed 2
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
*****Memory check*****
Returned 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 6 12 11 7 2 3 2 4 2 3 6 : 36360
aida02 : 21 15 7 3 2 3 1 4 2 3 6 : 35996
aida03 : 9 10 10 2 4 3 3 3 2 3 6 : 36052
aida04 : 17 17 17 4 0 2 3 4 2 3 6 : 36444
aida05 : 25 7 3 1 1 1 2 3 2 4 6 : 37292
aida06 : 29 15 7 2 3 4 1 3 3 3 6 : 36700
aida07 : 17 17 6 5 2 3 2 3 3 3 6 : 36812
aida08 : 22 6 10 5 3 1 3 4 2 3 6 : 36360
aida09 : 18 28 14 4 2 3 3 3 2 3 6 : 36232
aida10 : 26 16 4 3 3 1 3 4 2 3 6 : 36296
aida11 : 16 10 4 0 3 3 1 4 2 3 6 : 35856
aida12 : 19 14 4 2 4 4 1 3 3 3 6 : 36668
04:15 General Check
Rates, Tempratures, Voltages are ok, attached 5,6,7,8
******Clock Check*******
OK
Clock status test result: Passed 12, Failed 0
Understand status as follows
Status bit 3 : firmware PLL that creates clocks from external clock not locked
Status bit 2 : always logic '1'
Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock
Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock
If all these bits are not set then the operation of the firmware is unreliable
******ADC******
Clock status test result: Passed 12, Failed 0
Understand status as follows
Status bit 3 : firmware PLL that creates clocks from external clock not locked
Status bit 2 : always logic '1'
Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock
Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock
If all these bits are not set then the operation of the firmware is unreliable
******White Rabbit check******
Base Current Difference
aida01 fault 0x7686 : 0x768a : 4
aida02 fault 0x941d : 0x9421 : 4
aida03 fault 0x7cd7 : 0x7cdb : 4
aida04 fault 0xb86d : 0xb871 : 4
aida05 fault 0x1a59 : 0x1a61 : 8
aida06 fault 0x4f45 : 0x4f4d : 8
aida07 fault 0x3bfc : 0x3c39 : 61
aida08 fault 0xc7ce : 0xc7d5 : 7
aida09 fault 0xb33b : 0xb33c : 1
White Rabbit error counter test result: Passed 3, Failed 9
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
******FPGA Check******
Base Current Difference
aida09 fault 0x1 : 0x2 : 1
aida12 fault 0xa : 0x11 : 7
FPGA Timestamp error counter test result: Passed 10, Failed 2
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
****** Memorey check******
Returned 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 27 21 10 7 1 3 2 4 2 3 6 : 36436
aida02 : 28 21 3 3 1 3 1 4 2 3 6 : 35944
aida03 : 15 8 11 3 3 3 3 3 2 3 6 : 36044
aida04 : 25 19 14 4 1 3 4 3 2 3 6 : 36380
aida05 : 12 6 5 1 0 2 2 3 2 4 6 : 37328
aida06 : 29 21 4 2 3 4 1 3 3 3 6 : 36700
aida07 : 19 14 7 6 2 3 2 2 3 3 6 : 36332
aida08 : 11 8 8 6 3 1 3 4 2 3 6 : 36332
aida09 : 16 25 11 3 1 2 2 4 2 3 6 : 36184
aida10 : 14 13 4 2 3 2 2 4 2 3 6 : 36064
aida11 : 4 9 4 0 3 3 1 4 2 3 6 : 35800
aida12 : 38 17 4 2 4 4 1 3 3 3 6 : 36768
|
| Attachment 1: 210419_0302_Voltages.png
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| Attachment 2: 210419_0303_Stats.png
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| Attachment 3: 210419_0303_Temp.png
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| Attachment 4: 210419_0406_ucesb.png
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| Attachment 5: 210419_0402_Stats.png
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| Attachment 6: 210419_0402_Voltages.png
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| Attachment 7: 210419_0406_ucesb.png
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| Attachment 8: 210419_0414_ucesb.png
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|
242
|
Sun Apr 18 21:43:01 2021 |
ML-OH | system wide checks |
New System wide check 10pm CET
Clock status test result: Passed 12, Failed 0
Understand status as follows
Status bit 3 : firmware PLL that creates clocks from external clock not locked
Status bit 2 : always logic '1'
Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock
Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock
If all these bits are not set then the operation of the firmware is unreliable
ADC calibration check:
FEE64 module aida06 failed
FEE64 module aida07 failed
FEE64 module aida10 failed
Calibration test result: Passed 9, Failed 3
If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module
Base Current Difference
aida01 fault 0x7686 : 0x768a : 4
aida02 fault 0x941d : 0x9421 : 4
aida03 fault 0x7cd7 : 0x7cdb : 4
aida04 fault 0xb86d : 0xb871 : 4
aida05 fault 0x1a59 : 0x1a61 : 8
aida06 fault 0x4f45 : 0x4f4d : 8
aida07 fault 0x3bfc : 0x3c1d : 33
aida08 fault 0xc7ce : 0xc7d5 : 7
aida09 fault 0xb33b : 0xb33c : 1
White Rabbit error counter test result: Passed 3, Failed 9
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
FPGA timestamp error checks:
Base Current Difference
aida09 fault 0x1 : 0x2 : 1
aida12 fault 0xa : 0xf : 5
FPGA Timestamp error counter test result: Passed 10, Failed 2
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
Memory from FEE64:
Returned 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 22 19 6 4 2 3 2 4 2 3 6 : 36304
aida02 : 23 9 3 3 1 3 1 4 2 3 6 : 35828
aida03 : 15 5 6 3 2 3 3 3 2 3 6 : 35876
aida04 : 20 8 18 1 1 3 4 3 2 3 6 : 36240
aida05 : 21 7 1 2 1 2 4 3 2 3 6 : 35868
aida06 : 18 8 4 1 3 4 1 3 3 3 6 : 36520
aida07 : 4 9 3 4 2 3 2 2 3 3 6 : 36104
aida08 : 15 5 2 4 2 1 3 4 2 3 6 : 36100
aida09 : 2 23 8 1 2 3 2 4 2 3 6 : 36192
aida10 : 10 7 8 5 2 1 3 3 2 3 6 : 35712
aida11 : 1 9 5 1 2 3 1 4 2 3 6 : 35772
aida12 : 14 8 6 3 3 4 1 3 3 3 6 : 36600 |
| Attachment 1: 18-04-2021_10pm_HV.png
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| Attachment 2: 18-04-2021_10pm_StatGoodEvt.png
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| Attachment 3: 18-04-2021_10pm_PAUSE.png
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| Attachment 4: 18-04-2021_10pm_RESUME.png
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| Attachment 5: 18-04-2021_10pm_ADCdataItem.png
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| Attachment 6: 18-04-2021_10pm_DISC.png
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| Attachment 7: 18-04-2021_10pm_correlations.png
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| Attachment 8: 18-04-2021_10pm_SpecRate.png
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| Attachment 9: 18-04-2021_10pm_Spec1-8H.png
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| Attachment 10: 18-04-2021_10pm_Spec1-8HlayoutID6.png
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| Attachment 11: 18-04-2021_10pm_Spec1-8L.png
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| Attachment 12: 18-04-2021_10pm_Spec1-8L_layoutid4.png
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| Attachment 13: 18-04-2021_10pm_Spec1-8W.png
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| Attachment 14: 18-04-2021_10pm_SpecLayoutID8.png
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| Attachment 15: 18-04-2021_10pm_WR28-47.png
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| Attachment 16: 18-04-2021_10pm_WR48-63.png
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| Attachment 17: 18-04-2021_10pm_temp.png
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| Attachment 18: 18-04-2021_10pm_ucesb_monitor.png
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| Attachment 19: 18-04-2021_10pm-AIDA_Alerting_-_Grafana.png
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| Attachment 20: 18-04-2021_10pm_NewMerger.png
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|
241
|
Sun Apr 18 19:05:33 2021 |
ML-OH | All spectra reset |
All spectra reset at 8pm CET.
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|
|
240
|
Sun Apr 18 17:27:44 2021 |
ML-OH | system wide checks |
system wide checks at 6pm CET
##################################################
Difference noted from previous shift:
FPGS timestamp error 10 passed and 2 failed
##################################################
Clock status test result: Passed 12, Failed 0
Understand status as follows
Status bit 3 : firmware PLL that creates clocks from external clock not locked
Status bit 2 : always logic '1'
Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock
Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock
If all these bits are not set then the operation of the firmware is unreliable
ADC Calibration:
FEE64 module aida06 failed
FEE64 module aida07 failed
FEE64 module aida10 failed
Calibration test result: Passed 9, Failed 3
If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module
White Rabbit checks:
Base Current Difference
aida01 fault 0x7686 : 0x768a : 4
aida02 fault 0x941d : 0x9421 : 4
aida03 fault 0x7cd7 : 0x7cdb : 4
aida04 fault 0xb86d : 0xb871 : 4
aida05 fault 0x1a59 : 0x1a61 : 8
aida06 fault 0x4f45 : 0x4f4d : 8
aida07 fault 0x3bfc : 0x3c11 : 21
aida08 fault 0xc7ce : 0xc7d5 : 7
aida09 fault 0xb33b : 0xb33c : 1
White Rabbit error counter test result: Passed 3, Failed 9
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
FPGA timestamp errors checks:
Base Current Difference
aida09 fault 0x1 : 0x2 : 1
aida12 fault 0xa : 0xc : 2
FPGA Timestamp error counter test result: Passed 10, Failed 2
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
Memory information fro FEE64:
Returned 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 27 16 4 2 2 2 1 3 3 3 6 : 36332
aida02 : 19 8 9 3 2 2 2 4 2 3 6 : 36092
aida03 : 23 10 8 6 4 4 3 3 2 3 6 : 36332
aida04 : 27 4 8 0 1 3 4 3 2 3 6 : 36044
aida05 : 21 6 5 4 4 2 2 2 2 4 6 : 37204
aida06 : 23 11 5 0 3 4 1 3 3 3 6 : 36548
aida07 : 14 9 5 2 3 3 2 2 4 3 6 : 37200
aida08 : 26 8 7 2 2 1 4 3 2 3 6 : 35928
aida09 : 2 3 4 1 1 3 3 4 2 3 6 : 36160
aida10 : 16 9 2 5 1 1 3 4 2 3 6 : 36104
aida11 : 7 5 0 0 3 3 1 4 2 3 6 : 35716
aida12 : 9 7 3 2 4 4 1 3 3 3 6 : 36556
|
| Attachment 1: 18-04-2021_6pm_CAENHV.png
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| Attachment 2: 18-04-2021_6pm_StatGoodEvent.png
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| Attachment 3: 18-04-2021_6pm_ADCdataItem.png
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| Attachment 4: 18-04-2021_6pm_WR28-47#4.png
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| Attachment 5: 18-04-2021_6pm_WR48-63#5.png
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| Attachment 6: 18-04-2021_6pm_PauseInfo.png
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| Attachment 7: 18-04-2021_6pm_ResumeInfo.png
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| Attachment 8: 18-04-2021_6pm_DiscInfo.png
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| Attachment 9: 18-04-2021_6pm_Correlation#8.png
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| Attachment 10: 18-04-2021_6pm_ucesb.png
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| Attachment 11: 18-04-2021_645pm_tempScan.png
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| Attachment 12: 18-04-2021_645pm_Spec1-8L.png
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| Attachment 13: 18-04-2021_7pm_Spec1-8L_2.png
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| Attachment 14: 18-04-2021_7pm_Spec1-8_layoutId4.png
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| Attachment 15: 18-04-2021_7pm_Spec1-8H.png
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| Attachment 16: 18-04-2021_645pm_SpecRate.png
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| Attachment 17: 18-04-2021_730pm_AIDA_LC.png
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|
239
|
Sun Apr 18 11:18:21 2021 |
TD | Sunday 18 April 12.00-16.00 |
12.18 DAQ continues file NULL/R30_490
ASIC settings 2019Dec19-16.19.51
slow comparator 0x64 -> 0xa
BNC PB-5
amplitude 2V
attenuation 1x
decay time 1ms
frequency 2Hz
12.22 all histograms zero'd
c. 12.30 219Rn setting
12.35 analysis of R30_490 - see attachment 1
13.15 system wide checks
Clock status test result: Passed 12, Failed 0
Understand status as follows
Status bit 3 : firmware PLL that creates clocks from external clock not locked
Status bit 2 : always logic '1'
Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock
Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock
If all these bits are not set then the operation of the firmware is unreliable
FEE64 module aida06 failed
FEE64 module aida07 failed
FEE64 module aida10 failed
Calibration test result: Passed 9, Failed 3
If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module
Base Current Difference
aida01 fault 0x7686 : 0x768a : 4
aida02 fault 0x941d : 0x9421 : 4
aida03 fault 0x7cd7 : 0x7cdb : 4
aida04 fault 0xb86d : 0xb871 : 4
aida05 fault 0x1a59 : 0x1a5f : 6
aida06 fault 0x4f45 : 0x4f4b : 6
aida07 fault 0x3bfc : 0x3c04 : 8
aida08 fault 0xc7ce : 0xc7d4 : 6
aida09 fault 0xb33b : 0xb33c : 1
White Rabbit error counter test result: Passed 3, Failed 9
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
Base Current Difference
aida12 fault 0xa : 0xb : 1
FPGA Timestamp error counter test result: Passed 11, Failed 1
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
Returned 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 23 10 3 1 1 2 1 3 3 3 6 : 36156
aida02 : 2 11 7 4 2 2 2 4 2 3 6 : 36048
aida03 : 21 8 6 4 5 4 3 3 2 3 6 : 36276
aida04 : 19 11 14 3 2 3 2 4 2 3 6 : 36324
aida05 : 25 4 5 4 4 2 1 3 2 4 6 : 37460
aida06 : 13 9 15 1 3 5 1 3 3 3 6 : 36812
aida07 : 19 10 6 1 3 3 2 2 4 3 6 : 37212
aida08 : 23 6 4 2 1 1 3 4 2 3 6 : 36044
aida09 : 11 5 5 1 2 4 3 3 2 3 6 : 35908
aida10 : 14 5 6 5 3 1 3 3 2 3 6 : 35744
aida11 : 16 5 3 0 3 3 1 4 2 3 6 : 35800
aida12 : 12 10 0 2 4 4 1 3 3 3 6 : 36544
Collecting the file size of each FEE64 Options CONTENTS file to check they are all the same
FEE : aida01 => Options file size is 1025 Last changed Sat Apr 17 06:14:30 CEST 2021
FEE : aida02 => Options file size is 1014 Last changed Fri Apr 16 00:56:20 CEST 2021
FEE : aida03 => Options file size is 1014 Last changed Wed Apr 14 21:52:04 CEST 2021
FEE : aida04 => Options file size is 1025 Last changed Sat Apr 17 06:07:36 CEST 2021
FEE : aida05 => Options file size is 1025 Last changed Fri Apr 16 00:53:25 CEST 2021
FEE : aida06 => Options file size is 1014 Last changed Wed Apr 14 21:52:04 CEST 2021
FEE : aida07 => Options file size is 1014 Last changed Wed Apr 14 21:52:04 CEST 2021
FEE : aida08 => Options file size is 1014 Last changed Wed Apr 14 21:52:04 CEST 2021
FEE : aida09 => Options file size is 1014 Last changed Wed Apr 14 21:52:05 CEST 2021
FEE : aida10 => Options file size is 1014 Last changed Wed Apr 14 21:52:06 CEST 2021
FEE : aida11 => Options file size is 1014 Last changed Wed Apr 14 21:52:05 CEST 2021
FEE : aida12 => Options file size is 1025 Last changed Wed Apr 14 21:58:54 CEST 2021
*no faults detected by ~/oh/OptionsCheck.py
13.10 Detector biases & leakage currents OK - see attachment 2
Statistics - good events, adc data, disc data, info code 4 & 5, pause, resume, correlation info - attachments 3-12
per FEE64 rate spectra - attachments 13-14
1.8.L spectra - attachments 15-18
pulser peak widths
1 80
2 113
3 308
4 105
5 50
6 91
7 61
8 90
9 200
10 133
11 187
12 107
1.8.H spectra - attachments 19-20
1.8.W spectra - attachments 21-22
ucesb - attachment 23
implant rates DSSSD#1-3 to c. 1kHz
grafana - AIDA DSSSD leakage currents for previous 2 days - attachment 24
merger & merger/tape server/mbs data tranfser - attachment 25
no recent merger warning/error messages
13.30 225At setting |
| Attachment 1: R30_490
|
*** TDR format 3.3.0 analyser - TD - January 2019
*** ERROR: READ I/O error: 5002
blocks: 32000
ADC data format: 256516272 ( 1223332.2 Hz)
Other data format: 5403728 ( 25770.5 Hz)
Sample trace data format: 0 ( 0.0 Hz)
Undefined format: 0 ( 0.0 Hz)
Other data format type: PAUSE: 0 ( 0.0 Hz)
RESUME: 0 ( 0.0 Hz)
SYNC100: 32781 ( 156.3 Hz)
WR48-63: 32781 ( 156.3 Hz)
FEE64 disc: 828389 ( 3950.6 Hz)
MBS info: 4509777 ( 21507.2 Hz)
Other info: 0 ( 0.0 Hz)
ADC data range bit set: 263493 ( 1256.6 Hz)
Timewarps: ADC: 0 ( 0.0 Hz)
PAUSE: 0 ( 0.0 Hz)
RESUME: 0 ( 0.0 Hz)
SYNC100: 0 ( 0.0 Hz)
WR48-63: 0 ( 0.0 Hz)
FEE64 disc: 0 ( 0.0 Hz)
MBS info: 0 ( 0.0 Hz)
Undefined: 0 ( 0.0 Hz)
Sample trace: 0 ( 0.0 Hz)
*** Timestamp elapsed time: 209.687 s
FEE elapsed dead time(s) elapsed idle time(s)
1 0.000 76.433
2 0.000 87.604
3 0.000 78.795
4 0.000 195.707
5 0.000 158.854
6 0.000 193.755
7 0.000 152.656
8 0.000 23.126
9 0.000 23.243
10 0.000 11.178
11 0.000 108.457
12 0.000 0.000
13 0.000 0.000
14 0.000 0.000
15 0.000 0.000
16 0.000 0.000
17 0.000 0.000
18 0.000 0.000
19 0.000 0.000
20 0.000 0.000
21 0.000 0.000
22 0.000 0.000
23 0.000 0.000
24 0.000 0.000
25 0.000 0.000
26 0.000 0.000
27 0.000 0.000
28 0.000 0.000
29 0.000 0.000
30 0.000 0.000
31 0.000 0.000
32 0.000 0.000
*** Statistics
FEE ADC Data Other Data Sample Undefined Pause Resume SYNC100 WR48-63 Disc MBS Other HEC Data
0 9851554 72944 0 0 0 0 1261 1261 69168 1254 0 26448
1 21158309 48956 0 0 0 0 2701 2701 43554 0 0 16374
2 17027137 1992411 0 0 0 0 2376 2376 156273 1831386 0 25239
3 18790255 1894647 0 0 0 0 2567 2567 58490 1831023 0 23746
4 2269151 296174 0 0 0 0 339 339 74660 220836 0 26646
5 8373135 260125 0 0 0 0 1152 1152 43783 214038 0 16230
6 4256540 286725 0 0 0 0 532 532 81589 204072 0 25586
7 9526319 267328 0 0 0 0 1246 1246 57668 207168 0 22643
8 54059298 76554 0 0 0 0 6619 6619 63316 0 0 22746
9 49446691 53505 0 0 0 0 6256 6256 40993 0 0 14045
10 45199495 92635 0 0 0 0 5711 5711 81213 0 0 23246
11 16558388 61724 0 0 0 0 2021 2021 57682 0 0 20544
12 0 0 0 0 0 0 0 0 0 0 0 0
13 0 0 0 0 0 0 0 0 0 0 0 0
14 0 0 0 0 0 0 0 0 0 0 0 0
15 0 0 0 0 0 0 0 0 0 0 0 0
16 0 0 0 0 0 0 0 0 0 0 0 0
17 0 0 0 0 0 0 0 0 0 0 0 0
18 0 0 0 0 0 0 0 0 0 0 0 0
19 0 0 0 0 0 0 0 0 0 0 0 0
20 0 0 0 0 0 0 0 0 0 0 0 0
21 0 0 0 0 0 0 0 0 0 0 0 0
22 0 0 0 0 0 0 0 0 0 0 0 0
23 0 0 0 0 0 0 0 0 0 0 0 0
24 0 0 0 0 0 0 0 0 0 0 0 0
25 0 0 0 0 0 0 0 0 0 0 0 0
26 0 0 0 0 0 0 0 0 0 0 0 0
27 0 0 0 0 0 0 0 0 0 0 0 0
28 0 0 0 0 0 0 0 0 0 0 0 0
29 0 0 0 0 0 0 0 0 0 0 0 0
30 0 0 0 0 0 0 0 0 0 0 0 0
31 0 0 0 0 0 0 0 0 0 0 0 0
32 0 0 0 0 0 0 0 0 0 0 0 0
*** Timewarps
FEE ADC Pause Resume SYNC100 WR48-63 Disc MBS Undefined Samples
0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0
2 0 0 0 0 0 0 0 0 0
3 0 0 0 0 0 0 0 0 0
4 0 0 0 0 0 0 0 0 0
5 0 0 0 0 0 0 0 0 0
6 0 0 0 0 0 0 0 0 0
7 0 0 0 0 0 0 0 0 0
8 0 0 0 0 0 0 0 0 0
9 0 0 0 0 0 0 0 0 0
10 0 0 0 0 0 0 0 0 0
11 0 0 0 0 0 0 0 0 0
12 0 0 0 0 0 0 0 0 0
13 0 0 0 0 0 0 0 0 0
14 0 0 0 0 0 0 0 0 0
15 0 0 0 0 0 0 0 0 0
16 0 0 0 0 0 0 0 0 0
17 0 0 0 0 0 0 0 0 0
18 0 0 0 0 0 0 0 0 0
19 0 0 0 0 0 0 0 0 0
20 0 0 0 0 0 0 0 0 0
21 0 0 0 0 0 0 0 0 0
22 0 0 0 0 0 0 0 0 0
23 0 0 0 0 0 0 0 0 0
24 0 0 0 0 0 0 0 0 0
25 0 0 0 0 0 0 0 0 0
26 0 0 0 0 0 0 0 0 0
27 0 0 0 0 0 0 0 0 0
28 0 0 0 0 0 0 0 0 0
29 0 0 0 0 0 0 0 0 0
30 0 0 0 0 0 0 0 0 0
31 0 0 0 0 0 0 0 0 0
32 0 0 0 0 0 0 0 0 0
*** Program elapsed time:44645.059s ( 0.717 blocks/s, 0.045 Mb/s)
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| Attachment 2: 50.png
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| Attachment 3: Screenshot_2021-04-18_Statistics_aidas-gsi(1).png
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.png.png "Screenshot_2021-04-18_Statistics_aidas-gsi(1).png")
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| Attachment 4: Screenshot_2021-04-18_Temperature_and_status_scan_aidas-gsi(2).png
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.png.png "Screenshot_2021-04-18_Temperature_and_status_scan_aidas-gsi(2).png")
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| Attachment 5: Screenshot_2021-04-18_Statistics_aidas-gsi(2).png
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.png.png "Screenshot_2021-04-18_Statistics_aidas-gsi(2).png")
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| Attachment 6: Screenshot_2021-04-18_Statistics_aidas-gsi(3).png
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.png.png "Screenshot_2021-04-18_Statistics_aidas-gsi(3).png")
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| Attachment 7: Screenshot_2021-04-18_Statistics_aidas-gsi(4).png
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.png.png "Screenshot_2021-04-18_Statistics_aidas-gsi(4).png")
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| Attachment 8: Screenshot_2021-04-18_Statistics_aidas-gsi(5).png
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.png.png "Screenshot_2021-04-18_Statistics_aidas-gsi(5).png")
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| Attachment 9: Screenshot_2021-04-18_Statistics_aidas-gsi(6).png
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.png.png "Screenshot_2021-04-18_Statistics_aidas-gsi(6).png")
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| Attachment 10: Screenshot_2021-04-18_Statistics_aidas-gsi(7).png
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.png.png "Screenshot_2021-04-18_Statistics_aidas-gsi(7).png")
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| Attachment 11: Screenshot_2021-04-18_Statistics_aidas-gsi(8).png
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.png.png "Screenshot_2021-04-18_Statistics_aidas-gsi(8).png")
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| Attachment 12: Screenshot_2021-04-18_Statistics_aidas-gsi(9).png
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.png.png "Screenshot_2021-04-18_Statistics_aidas-gsi(9).png")
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| Attachment 13: Screenshot_2021-04-18_Spectrum_Browser_aidas-gsi.png
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| Attachment 14: Screenshot_2021-04-18_Spectrum_Browser_aidas-gsi(1).png
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.png.png "Screenshot_2021-04-18_Spectrum_Browser_aidas-gsi(1).png")
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| Attachment 15: Screenshot_2021-04-18_Spectrum_Browser_aidas-gsi(2).png
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.png.png "Screenshot_2021-04-18_Spectrum_Browser_aidas-gsi(2).png")
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| Attachment 16: Screenshot_2021-04-18_Spectrum_Browser_aidas-gsi(3).png
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.png.png "Screenshot_2021-04-18_Spectrum_Browser_aidas-gsi(3).png")
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| Attachment 17: Screenshot_2021-04-18_Spectrum_Browser_aidas-gsi(4).png
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.png.png "Screenshot_2021-04-18_Spectrum_Browser_aidas-gsi(4).png")
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| Attachment 18: Screenshot_2021-04-18_Spectrum_Browser_aidas-gsi(5).png
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.png.png "Screenshot_2021-04-18_Spectrum_Browser_aidas-gsi(5).png")
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| Attachment 19: Screenshot_2021-04-18_Spectrum_Browser_aidas-gsi(6).png
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.png.png "Screenshot_2021-04-18_Spectrum_Browser_aidas-gsi(6).png")
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| Attachment 20: Screenshot_2021-04-18_Spectrum_Browser_aidas-gsi(7).png
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.png.png "Screenshot_2021-04-18_Spectrum_Browser_aidas-gsi(7).png")
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| Attachment 21: Screenshot_2021-04-18_Spectrum_Browser_aidas-gsi(8).png
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.png.png "Screenshot_2021-04-18_Spectrum_Browser_aidas-gsi(8).png")
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| Attachment 22: Screenshot_2021-04-18_Spectrum_Browser_aidas-gsi(9).png
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.png.png "Screenshot_2021-04-18_Spectrum_Browser_aidas-gsi(9).png")
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| Attachment 23: Screenshot_2021-04-18_ucesb.png
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| Attachment 24: Screenshot_2021-04-18_AIDA_Alerting_-_Grafana.png
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| Attachment 25: 51.png
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238
|
Sun Apr 18 07:30:20 2021 |
DJ, TD | Sunday 18th April 08:00-12:00 |
---- 09-26
FEE64 module aida06 failed
FEE64 module aida07 failed
FEE64 module aida10 failed
Calibration test result: Passed 9, Failed 3
If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module
---
Base Current Difference
aida01 fault 0x7685 : 0x7686 : 1
aida02 fault 0x941c : 0x941d : 1
aida03 fault 0x7cd6 : 0x7cd7 : 1
aida04 fault 0xb86c : 0xb86d : 1
aida05 fault 0x1a52 : 0x1a59 : 7
aida06 fault 0x4f3e : 0x4f45 : 7
aida07 fault 0x3bcd : 0x3bfc : 47
aida08 fault 0xc7c7 : 0xc7ce : 7
aida09 fault 0xb33a : 0xb33b : 1
White Rabbit error counter test result: Passed 3, Failed 9
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
--
Base Current Difference
aida01 fault 0x7685 : 0x7686 : 1
aida02 fault 0x941c : 0x941d : 1
aida03 fault 0x7cd6 : 0x7cd7 : 1
aida04 fault 0xb86c : 0xb86d : 1
aida05 fault 0x1a52 : 0x1a59 : 7
aida06 fault 0x4f3e : 0x4f45 : 7
aida07 fault 0x3bcd : 0x3bfc : 47
aida08 fault 0xc7c7 : 0xc7ce : 7
aida09 fault 0xb33a : 0xb33b : 1
White Rabbit error counter test result: Passed 3, Failed 9
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
-
Base Current Difference
aida01 fault 0x7685 : 0x7686 : 1
aida02 fault 0x941c : 0x941d : 1
aida03 fault 0x7cd6 : 0x7cd7 : 1
aida04 fault 0xb86c : 0xb86d : 1
aida05 fault 0x1a52 : 0x1a59 : 7
aida06 fault 0x4f3e : 0x4f45 : 7
aida07 fault 0x3bcd : 0x3bfc : 47
aida08 fault 0xc7c7 : 0xc7ce : 7
aida09 fault 0xb33a : 0xb33b : 1
White Rabbit error counter test result: Passed 3, Failed 9
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
08.45 TD resets baseline for WR and FPGA errors
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| Attachment 1: Screenshot_2021-04-18_Statistics_aidas-gsi.png
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| Attachment 2: Screenshot_2021-04-18_Temperature_and_status_scan_aidas-gsi.png
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| Attachment 3: 52.png
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| Attachment 4: 53.png
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| Attachment 5: Screenshot_2021-04-18_Temperature_and_status_scan_aidas-gsi(1).png
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.png.png "Screenshot_2021-04-18_Temperature_and_status_scan_aidas-gsi(1).png")
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| Attachment 6: 54.png
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| Attachment 7: Screenshot_2021-04-18_Statistics_aidas-gsi(1).png
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.png.png "Screenshot_2021-04-18_Statistics_aidas-gsi(1).png")
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237
|
Sun Apr 18 00:57:36 2021 |
BA, MA | Sanday 18 April 00.00-08.00 |
02:01 Beam has stopped at 01:37 and returend at 01:43 for few min and then stopped again and not knowen how it will take until it is back
AIDA scalers attached 1
statistic attached 2
temretuer attached 3
bias attached 4
Clock check ok
ADC check :
FEE64 module aida06 failed
FEE64 module aida07 failed
FEE64 module aida10 failed
Calibration test result: Passed 9, Failed 3
If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module
Base Current Difference
aida05 fault 0x1a52 : 0x1a55 : 3
aida06 fault 0x4f3e : 0x4f41 : 3
aida07 fault 0x3bcd : 0x3bea : 29
aida08 fault 0xc7c7 : 0xc7ca : 3
White Rabbit error counter test result: Passed 8, Failed 4
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
Base Current Difference
aida09 fault 0x0 : 0x1 : 1
aida12 fault 0x0 : 0x9 : 9
FPGA Timestamp error counter test result: Passed 10, Failed 2
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
Returned 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 32 8 3 1 0 3 1 3 3 3 6 : 36240
aida02 : 11 7 9 3 1 2 2 4 2 3 6 : 35988
aida03 : 32 4 13 5 5 4 3 3 2 3 6 : 36432
aida04 : 26 7 6 1 2 3 2 4 2 3 6 : 36128
aida05 : 18 8 8 7 4 2 2 2 2 4 6 : 37352
aida06 : 24 11 3 1 2 5 1 3 3 3 6 : 36616
aida07 : 14 5 3 3 3 2 3 2 4 3 6 : 37296
aida08 : 21 7 1 5 0 1 2 3 3 3 6 : 36284
aida09 : 0 7 1 1 1 3 2 2 3 3 6 : 35880
aida10 : 22 5 3 4 1 2 2 2 3 3 6 : 35952
aida11 : 4 3 1 1 2 2 3 3 2 3 6 : 35544
aida12 : 22 10 5 4 4 4 1 3 3 3 6 : 36728
02:19 beam is back
03:58 The beam has not been stable yet
The rate reach 1.5 kHz, they will contact FRS team to lower the intensity of the beam
AIDA scalers attached 8
statistic attached 7
temretuer attached 6
bias attached 5
FEE64 module aida06 failed
FEE64 module aida07 failed
FEE64 module aida10 failed
Calibration test result: Passed 9, Failed 3
If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module
Base Current Difference
aida05 fault 0x1a52 : 0x1a55 : 3
aida06 fault 0x4f3e : 0x4f41 : 3
aida07 fault 0x3bcd : 0x3beb : 30
aida08 fault 0xc7c7 : 0xc7ca : 3
White Rabbit error counter test result: Passed 8, Failed 4
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
Base Current Difference
aida09 fault 0x0 : 0x1 : 1
aida12 fault 0x0 : 0x9 : 9
FPGA Timestamp error counter test result: Passed 10, Failed 2
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
Returned 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 21 8 6 2 1 2 1 3 3 3 6 : 36212
aida02 : 24 14 14 2 1 2 2 4 2 3 6 : 36144
aida03 : 31 5 10 5 5 4 2 3 2 3 6 : 36132
aida04 : 12 11 12 2 2 2 3 4 2 3 6 : 36360
aida05 : 23 8 5 7 4 2 2 2 2 4 6 : 37324
aida06 : 21 14 14 1 3 5 1 3 3 3 6 : 36868
aida07 : 15 9 5 0 3 2 3 2 4 3 6 : 37268
aida08 : 21 11 10 3 0 1 2 3 3 3 6 : 36396
aida09 : 5 7 5 1 1 3 1 3 3 3 6 : 36220
aida10 : 15 13 12 3 2 1 2 2 3 3 6 : 36036
aida11 : 13 10 1 0 2 2 2 4 2 3 6 : 35860
aida12 : 29 5 4 5 5 3 1 3 3 3 6 : 36668
05: 07 The rate was a bout 1500 and 2000, we contacted Oscar he said (if it's just bursts it should be ok), so they decided to do nothing.
06:26
AIDA scalers attached 9
statistic attached 10
temretuer attached 11
bias attached 12
Clock status test result: Passed 12, Failed 0
Understand status as follows
Status bit 3 : firmware PLL that creates clocks from external clock not locked
Status bit 2 : always logic '1'
Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock
Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock
If all these bits are not set then the operation of the firmware is unreliable
FEE64 module aida06 failed
FEE64 module aida07 failed
FEE64 module aida10 failed
Calibration test result: Passed 9, Failed 3
If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module
Base Current Difference
aida01 fault 0x7685 : 0x7686 : 1
aida02 fault 0x941c : 0x941d : 1
aida03 fault 0x7cd6 : 0x7cd7 : 1
aida04 fault 0xb86c : 0xb86d : 1
aida05 fault 0x1a52 : 0x1a59 : 7
aida06 fault 0x4f3e : 0x4f45 : 7
aida07 fault 0x3bcd : 0x3bf9 : 44
aida08 fault 0xc7c7 : 0xc7ce : 7
aida09 fault 0xb33a : 0xb33b : 1
White Rabbit error counter test result: Passed 3, Failed 9
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
Base Current Difference
aida09 fault 0x0 : 0x1 : 1
aida12 fault 0x0 : 0xa : 10
FPGA Timestamp error counter test result: Passed 10, Failed 2
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
Returned 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 17 12 6 2 1 2 1 3 3 3 6 : 36228
aida02 : 19 11 12 3 2 2 2 4 2 3 6 : 36164
aida03 : 25 8 12 5 4 4 3 3 2 3 6 : 36356
aida04 : 22 19 11 3 1 2 3 4 2 3 6 : 36416
aida05 : 35 6 5 6 3 2 2 2 3 3 6 : 36236
aida06 : 12 11 11 2 3 4 1 3 3 3 6 : 36664
aida07 : 18 6 2 1 3 2 3 2 3 3 6 : 36216
aida08 : 27 10 8 3 0 1 2 3 3 3 6 : 36380
aida09 : 18 6 6 1 0 2 2 2 3 3 6 : 35832
aida10 : 3 14 10 3 1 1 2 3 3 3 6 : 36412
aida11 : 1 3 2 0 2 2 2 4 2 3 6 : 35772
aida12 : 0 5 6 3 3 4 1 3 3 3 6 : 36520
07:57 The beam stopped and they said there is a water leak !
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| Attachment 1: 20210418_0154.png
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| Attachment 2: 20210418_0152_rate.png
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| Attachment 3: 20210418_0150_tem.png
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| Attachment 4: 20210418_0150_bias.png
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| Attachment 5: 20210418_0407.png
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| Attachment 6: 20210418_0409.png
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| Attachment 7: 20210418_0411.png
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| Attachment 8: 20210418_0413.png
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| Attachment 9: 18042021_0722_AIDA.png
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| Attachment 10: 18042021_0615_rate.png
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| Attachment 11: 18042021_0616_temp.png
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| Attachment 12: 18042021_0620_bias.png
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236
|
Sat Apr 17 19:39:56 2021 |
DJ, TD | Saturday 17 April 20.00-00.00 |
19.37 per FEE64 rate spectra - attachments 1 & 2
1.8.L spectra - attachments 3 & 4
1.8.H spectra - attachments 5-8
1.8.W spectra - attachments 9 & 10
20.42 DAQ contrinues file NULL/R30_233
Base Current Difference
aida05 fault 0x1a52 : 0x1a55 : 3
aida06 fault 0x4f3e : 0x4f41 : 3
aida07 fault 0x3bcd : 0x3bd7 : 10
aida08 fault 0xc7c7 : 0xc7ca : 3
White Rabbit error counter test result: Passed 8, Failed 4
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
Base Current Difference
aida09 fault 0x0 : 0x1 : 1
aida12 fault 0x0 : 0x4 : 4
FPGA Timestamp error counter test result: Passed 10, Failed 2
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
-------
23:48
Clock status test result: Passed 12, Failed 0
Understand status as follows
Status bit 3 : firmware PLL that creates clocks from external clock not locked
Status bit 2 : always logic '1'
Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock
Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock
If all these bits are not set then the operation of the firmware is unreliable
FEE64 module aida06 failed
FEE64 module aida07 failed
FEE64 module aida10 failed
Calibration test result: Passed 9, Failed 3
If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module
Base Current Difference
aida05 fault 0x1a52 : 0x1a55 : 3
aida06 fault 0x4f3e : 0x4f41 : 3
aida07 fault 0x3bcd : 0x3bde : 17
aida08 fault 0xc7c7 : 0xc7ca : 3
White Rabbit error counter test result: Passed 8, Failed 4
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
Base Current Difference
aida09 fault 0x0 : 0x1 : 1
aida12 fault 0x0 : 0x7 : 7
FPGA Timestamp error counter test result: Passed 10, Failed 2
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
Returned 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 26 5 6 2 1 3 1 3 3 3 6 : 36336
aida02 : 7 9 10 3 2 2 2 4 2 3 6 : 36068
aida03 : 26 7 8 4 3 4 2 4 2 3 6 : 36448
aida04 : 18 8 2 1 2 2 3 4 2 3 6 : 36168
aida05 : 24 7 9 4 3 1 3 2 2 4 6 : 37352
aida06 : 17 10 3 1 3 5 1 3 3 3 6 : 36644
aida07 : 7 11 2 2 3 2 3 2 4 3 6 : 37268
aida08 : 23 4 1 5 1 1 2 3 3 3 6 : 36332
aida09 : 14 6 3 2 1 3 2 3 3 3 6 : 36504
aida10 : 2 2 2 2 1 2 2 2 3 3 6 : 35768
aida11 : 2 2 1 2 2 2 2 4 2 3 6 : 35816
aida12 : 26 8 5 5 4 3 1 3 3 3 6 : 36632
---- |
| Attachment 1: Screenshot_2021-04-17_Spectrum_Browser_aidas-gsi.png
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| Attachment 2: Screenshot_2021-04-17_Spectrum_Browser_aidas-gsi(1).png
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.png.png "Screenshot_2021-04-17_Spectrum_Browser_aidas-gsi(1).png")
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| Attachment 3: Screenshot_2021-04-17_Spectrum_Browser_aidas-gsi(2).png
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.png.png "Screenshot_2021-04-17_Spectrum_Browser_aidas-gsi(2).png")
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| Attachment 4: Screenshot_2021-04-17_Spectrum_Browser_aidas-gsi(3).png
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.png.png "Screenshot_2021-04-17_Spectrum_Browser_aidas-gsi(3).png")
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| Attachment 5: Screenshot_2021-04-17_Spectrum_Browser_aidas-gsi(4).png
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.png.png "Screenshot_2021-04-17_Spectrum_Browser_aidas-gsi(4).png")
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| Attachment 6: Screenshot_2021-04-17_Spectrum_Browser_aidas-gsi(5).png
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.png.png "Screenshot_2021-04-17_Spectrum_Browser_aidas-gsi(5).png")
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| Attachment 7: Screenshot_2021-04-17_Spectrum_Browser_aidas-gsi(6).png
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.png.png "Screenshot_2021-04-17_Spectrum_Browser_aidas-gsi(6).png")
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| Attachment 8: Screenshot_2021-04-17_Spectrum_Browser_aidas-gsi(7).png
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.png.png "Screenshot_2021-04-17_Spectrum_Browser_aidas-gsi(7).png")
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| Attachment 9: Screenshot_2021-04-17_Spectrum_Browser_aidas-gsi(8).png
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.png.png "Screenshot_2021-04-17_Spectrum_Browser_aidas-gsi(8).png")
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| Attachment 10: Screenshot_2021-04-17_Statistics_aidas-gsi(4).png
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.png.png "Screenshot_2021-04-17_Statistics_aidas-gsi(4).png")
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| Attachment 11: Screenshot_2021-04-17_Temperature_and_status_scan_aidas-gsi(4).png
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.png.png "Screenshot_2021-04-17_Temperature_and_status_scan_aidas-gsi(4).png")
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| Attachment 12: 50.png
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| Attachment 13: 51.png
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235
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Sat Apr 17 15:29:27 2021 |
MS | Saturday 17 April 16:00-20:00 2021 |
16:21
FEE64 module aida06 failed
FEE64 module aida07 failed
FEE64 module aida10 failed
Calibration test result: Passed 9, Failed 3
If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module
Base Current Difference
aida05 fault 0x1a52 : 0x1a53 : 1
aida06 fault 0x4f3e : 0x4f3f : 1
aida07 fault 0x3bcd : 0x3bcf : 2
aida08 fault 0xc7c7 : 0xc7c8 : 1
White Rabbit error counter test result: Passed 8, Failed 4
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
Base Current Difference
aida09 fault 0x0 : 0x1 : 1
aida12 fault 0x0 : 0x2 : 2
FPGA Timestamp error counter test result: Passed 10, Failed 2
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
Collecting the file size of each FEE64 Options CONTENTS file to check they are all the same
FEE : aida01 => Options file size is 1025 Last changed Sat Apr 17 06:14:30 CEST 2021
FEE : aida02 => Options file size is 1014 Last changed Fri Apr 16 00:56:20 CEST 2021
FEE : aida03 => Options file size is 1014 Last changed Wed Apr 14 21:52:04 CEST 2021
FEE : aida04 => Options file size is 1025 Last changed Sat Apr 17 06:07:36 CEST 2021
FEE : aida05 => Options file size is 1025 Last changed Fri Apr 16 00:53:25 CEST 2021
FEE : aida06 => Options file size is 1014 Last changed Wed Apr 14 21:52:04 CEST 2021
FEE : aida07 => Options file size is 1014 Last changed Wed Apr 14 21:52:04 CEST 2021
FEE : aida08 => Options file size is 1014 Last changed Wed Apr 14 21:52:04 CEST 2021
FEE : aida09 => Options file size is 1014 Last changed Wed Apr 14 21:52:05 CEST 2021
FEE : aida10 => Options file size is 1014 Last changed Wed Apr 14 21:52:06 CEST 2021
FEE : aida11 => Options file size is 1014 Last changed Wed Apr 14 21:52:05 CEST 2021
FEE : aida12 => Options file size is 1025 Last changed Wed Apr 14 21:58:54 CEST 2021
18:29
Clock status test result: Passed 12, Failed 0
Understand status as follows
Status bit 3 : firmware PLL that creates clocks from external clock not locked
Status bit 2 : always logic '1'
Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock
Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock
If all these bits are not set then the operation of the firmware is unreliable
FEE64 module aida06 failed
FEE64 module aida07 failed
FEE64 module aida10 failed
Calibration test result: Passed 9, Failed 3
If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module
Base Current Difference
aida05 fault 0x1a52 : 0x1a53 : 1
aida06 fault 0x4f3e : 0x4f3f : 1
aida07 fault 0x3bcd : 0x3bd1 : 4
aida08 fault 0xc7c7 : 0xc7c8 : 1
White Rabbit error counter test result: Passed 8, Failed 4
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
Base Current Difference
aida09 fault 0x0 : 0x1 : 1
aida12 fault 0x0 : 0x2 : 2
FPGA Timestamp error counter test result: Passed 10, Failed 2
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
Returned 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 21 3 4 4 1 3 1 3 3 3 6 : 36332
aida02 : 4 3 13 2 2 3 2 4 2 3 6 : 36152
aida03 : 12 7 5 2 2 3 2 4 2 3 6 : 36088
aida04 : 17 6 9 5 1 1 2 3 3 3 6 : 36452
aida05 : 26 8 0 3 1 1 2 3 3 3 6 : 36296
aida06 : 22 6 9 4 3 4 2 3 3 3 6 : 36952
aida07 : 17 7 3 1 2 3 3 2 3 3 6 : 36300
aida08 : 24 5 4 4 1 1 2 3 3 3 6 : 36360
aida09 : 15 11 3 2 1 3 1 3 3 3 6 : 36292
aida10 : 2 3 5 2 1 2 2 2 3 3 6 : 35824
aida11 : 2 2 0 0 3 2 2 4 2 3 6 : 35800
aida12 : 18 15 7 5 4 3 1 3 3 3 6 : 36688
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| Attachment 1: 40.png
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| Attachment 2: Screenshot_2021-04-17_Statistics_aidas-gsi(2).png
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.png.png "Screenshot_2021-04-17_Statistics_aidas-gsi(2).png")
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| Attachment 3: Screenshot_2021-04-17_Temperature_and_status_scan_aidas-gsi(2).png
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.png.png "Screenshot_2021-04-17_Temperature_and_status_scan_aidas-gsi(2).png")
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| Attachment 4: Screenshot_2021-04-17_Statistics_aidas-gsi(3).png
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.png.png "Screenshot_2021-04-17_Statistics_aidas-gsi(3).png")
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| Attachment 5: Screenshot_2021-04-17_Temperature_and_status_scan_aidas-gsi(3).png
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.png.png "Screenshot_2021-04-17_Temperature_and_status_scan_aidas-gsi(3).png")
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| Attachment 6: 41.png
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234
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Sat Apr 17 11:27:38 2021 |
JS, TD | Saturday 17th April 12:00-16:00 |
Base Current Difference
aida05 fault 0x1a52 : 0x1a53 : 1
aida06 fault 0x4f3e : 0x4f3f : 1
aida07 fault 0x3bcd : 0x3bce : 1
aida08 fault 0xc7c7 : 0xc7c8 : 1
White Rabbit error counter test result: Passed 8, Failed 4
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
13:55 CEST
Statistics : ok elog:234/4
Temp : ok elog:234/5
Bias : ok elog:234/6
ucesb : ok
DB: No faults found
ADC Calibration check:
FEE64 module aida06 failed
FEE64 module aida07 failed
FEE64 module aida10 failed
Calibration test result: Passed 9, Failed 3
If any modules fail calibration , check the clock status and open the FADC Align and
Control browser page to rerun calibration for that module
White Rabbit Check:
Base Current Difference
aida05 fault 0x1a52 : 0x1a53 : 1
aida06 fault 0x4f3e : 0x4f3f : 1
aida07 fault 0x3bcd : 0x3bcf : 2
aida08 fault 0xc7c7 : 0xc7c8 : 1
White Rabbit error counter test result: Passed 8, Failed 4
FPGA check:
Base Current Difference
aida09 fault 0x0 : 0x1 : 1
aida12 fault 0x0 : 0x2 : 2
FPGA Timestamp error counter test result: Passed 10, Failed 2
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
14:05 no beam
14:10 beam back
14:15 no beam, beam current being optimised, going to thicker degrader when beam returns
14:37 CEST
Statistics : ok
Temp : ok
Bias : ok (ch3 now over 6uA)
ucesb : ok
DB: No faults found
15:03 CEST
Statistics : ok
Temp : ok
Bias : ok
ucesb : ok
DB: No faults found
15:31 CEST
Statistics : ok
Temp : ok
Bias : ok
ucesb : ok
DB: No faults found
15:50
Statistics : ok elog:234/7
Temp : ok elog:234/8
Bias : ok elog:234/9
ucesb : ok elog:234/10
DB: No faults found
ADC Calibration check:
FEE64 module aida06 failed
FEE64 module aida07 failed
FEE64 module aida10 failed
Calibration test result: Passed 9, Failed 3
If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module
White Rabbit Check:
Base Current Difference
aida05 fault 0x1a52 : 0x1a53 : 1
aida06 fault 0x4f3e : 0x4f3f : 1
aida07 fault 0x3bcd : 0x3bcf : 2
aida08 fault 0xc7c7 : 0xc7c8 : 1
White Rabbit error counter test result: Passed 8, Failed 4
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
FPGA check:
Base Current Difference
aida09 fault 0x0 : 0x1 : 1
aida12 fault 0x0 : 0x2 : 2
FPGA Timestamp error counter test result: Passed 10, Failed 2
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last |
| Attachment 1: 30.png
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| Attachment 2: Screenshot_2021-04-17_Statistics_aidas-gsi(3).png
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.png.png "Screenshot_2021-04-17_Statistics_aidas-gsi(3).png")
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| Attachment 3: Screenshot_2021-04-17_Temperature_and_status_scan_aidas-gsi(3).png
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.png.png "Screenshot_2021-04-17_Temperature_and_status_scan_aidas-gsi(3).png")
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| Attachment 4: Screenshot_2021-04-17_Statistics_aidas-gsi.png
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| Attachment 5: Screenshot_2021-04-17_Temperature_and_status_scan_aidas-gsi.png
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| Attachment 6: 31.png
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| Attachment 7: Screenshot_2021-04-17_Statistics_aidas-gsi(1).png
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.png.png "Screenshot_2021-04-17_Statistics_aidas-gsi(1).png")
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| Attachment 8: Screenshot_2021-04-17_Temperature_and_status_scan_aidas-gsi(1).png
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.png.png "Screenshot_2021-04-17_Temperature_and_status_scan_aidas-gsi(1).png")
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| Attachment 9: 32.png
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| Attachment 10: 33.png
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233
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Sat Apr 17 07:28:02 2021 |
LPG, TD | Saturday 08:00 - 12:00 |
08:30 CEST
HV and leakage currents: elog:233/1
Detector rates: elog:233/2
Temperatures: elog:233/3
WR status:
FEE64 module aida06 failed
FEE64 module aida07 failed
FEE64 module aida10 failed
Calibration test result: Passed 9, Failed 3
If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module
FPGA status:
Base Current Difference
aida12 fault 0x0 : 0x1 : 1
FPGA Timestamp error counter test result: Passed 11, Failed 1
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
09:20 CEST
Stats: ok!
DB: No faults found
ucesb: ok!
09:40 CEST
Beam will be stopped in order to increase intensity. Expected to be around 3-4 hours.
For now, we still get implants when Beam spill is on. Seems to be fluctuating as they play around.
10:00 CEST
Still getting beam, it is fluctuating in intensity
Stats: ok!
DB: No faults found
ucesb: ok!
HV and leakage currents: elog:233/4
Detector rates: elog:233/5
Temperatures: elog:233/6
Clock check: ok!
ADC calibration:
FEE64 module aida06 failed
FEE64 module aida07 failed
FEE64 module aida10 failed
Calibration test result: Passed 9, Failed 3
WR check: ok!
FPGA check:
Base Current Difference
aida12 fault 0x0 : 0x1 : 1
FPGA Timestamp error counter test result: Passed 11, Failed 1
Memory check: ok!
10:40 CEST
Stats: ok!
DB: No faults found
ucesb: ok!
11:00 CEST
Stats: ok!
DB: No faults found
ucesb: ok!
11:30 CEST
Stats: ok!
DB: No faults found
ucesb: ok!
12:00 BST
Stats: ok!
DB: No faults found
ucesb: ok!
HV and leakage currents: elog:233/7
Detector rates: elog:233/8
Temperatures: elog:233/9
Clock check: ok!
ADC calibration:
FEE64 module aida06 failed
FEE64 module aida07 failed
FEE64 module aida10 failed
Calibration test result: Passed 9, Failed 3
WR check:
Base Current Difference
aida05 fault 0x1a52 : 0x1a53 : 1
aida06 fault 0x4f3e : 0x4f3f : 1
aida07 fault 0x3bcd : 0x3bce : 1
aida08 fault 0xc7c7 : 0xc7c8 : 1
White Rabbit error counter test result: Passed 8, Failed 4
FPGA check:
Base Current Difference
aida09 fault 0x0 : 0x1 : 1
aida12 fault 0x0 : 0x2 : 2
Memory check: ok! |
| Attachment 1: 20.png
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| Attachment 2: Screenshot_2021-04-17_Statistics_aidas-gsi.png
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| Attachment 3: Screenshot_2021-04-17_Temperature_and_status_scan_aidas-gsi.png
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| Attachment 4: 21.png
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| Attachment 5: Screenshot_2021-04-17_Statistics_aidas-gsi(1).png
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| Attachment 6: Screenshot_2021-04-17_Temperature_and_status_scan_aidas-gsi(1).png
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| Attachment 7: 22.png
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| Attachment 8: Screenshot_2021-04-17_Statistics_aidas-gsi(2).png
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| Attachment 9: Screenshot_2021-04-17_Temperature_and_status_scan_aidas-gsi(2).png
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.png.png "Screenshot_2021-04-17_Temperature_and_status_scan_aidas-gsi(2).png")
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