 Wed Jul 23 15:56:00 2025, CC, MP, NK, Test of AIDA05 with new bias module 
|
Attachment1: AIDA05.1.8L when AIDA05 connected, biased at 101 V with shielded cables. BB7 is still connected but not biased (same configuration as the
previous elog). The channel of the CAEN power supply #0 is connected to ASIC08 and biased at 100V. The channel of the CAEN power supply #1 is disconnected
but still biased at 100V. AIDA04 (chained to AIDA05) is biased via a shielded cable to an iseg NHQ 246L power supplied, biased at 101 V with 16 uA. |
|
Wed Jul 23 15:04:26 2025, CC, MP, NK, Test of AIDA05 with BB7 connected to Mesytec but not biased
|
Attachment1: AIDA05.1.8L when AIDA05 connected, biased at 100 V with not-shielded cables, after the DEGAS platform has been closed, the 2 tiles of BB7
have been connected to the mesytec preamps. BB7 is not biased. The mesytec preamps have been fully connected and supplied but 6/8 black cables are not
connected on the other side. 4X and 4Y are connected to the 2 FEBEX cards. |
|
Sun May 9 19:29:23 2021, TD, Sunday 9 May 14x
|
| |
|
Sat Jun 8 23:00:52 2024, TD, Sunday 9 June 16x
|
23.58 8.6.24
|
|
Sun May 8 15:10:45 2022, TD, Sunday 8 May 6x
|
DSSSD bias and FEE64 power OFF during Ge install
|
|
Sat Mar 6 23:37:22 2021, TD, Sunday 7 March 00.00-08:00 18x
|
00.30 UNILAC problem - no beam
|
|
Sun Apr 7 18:13:56 2024, TD, Sunday 7 April contd. 6x
|
19.10 CAEN N1419ET LK fitted
power cycle
|
|
Sun Apr 7 12:02:23 2024, TD, Sunday 7 April 46x
|
13.00 Cooling water temperature and flow OK - attachment 1
|
|
Sun Jun 6 14:15:05 2021, TD, Sunday 6 June 9x
|
14.15 DAQ continues file S496/R32_117
Hot HEC channels multiple FEE64s from c. 06.00 this morning
ASIC check fixes
|
|
Sun May 5 10:22:24 2024, TD, Sunday 5 May
|
11.22 DSSSD#1 bias -120V leakage current -17.1uA
DSSSD#2 bias -120V leakage current -10.6uA
|
|
Sun May 30 08:57:53 2021, TD, Sunday 30 May 9x
|
09.55 DAQ continues - file S496/R18_588
alpha background
|
|
Sun Mar 3 16:06:11 2024, TD, Sunday 3 March 24x
|
17.00 FEE64 41:a0:71 ASIC #2 u/s
Replaced ASIC mezzanine with new ASIC mezzanine
|
|
Sun Apr 3 10:56:11 2022, TD, Sunday 3 April 35x
|
all system wide checks OK *except* aida10 failed ADC calibration
|
|
Sun Jun 26 08:51:20 2022, OH, NH, Sunday 26 June 08:00-24:00 27x
|
09:51 Taken over from Tom following the night shift
Experiment is still running smoothly
Compression of the files is complete up to the start of R5.
|
|
Sat Jun 25 22:48:57 2022, TD, Sunday 26 June 00:00-08:00 30x
|
23.43 Check ASIC control
Zero stats & all histograms
|
|
Sun Apr 25 10:22:16 2021, TD, Sunday 25 April 9x
|
11.25 All system wide checks OK *except*
Base Current Difference
|
|
Sat May 22 23:40:32 2021, TD, Sunday 23 May
|
00.40 Unable to connect to FEE64s 1-7
DAQ power cycled OK
|
|
Sun May 22 14:12:55 2022, TD, Sunday 22 May
|
15.11 DAQ stopped
Attachment 1 - DSSSD bias & leakage current
|
|
Sun Apr 21 00:34:33 2024, TD, Sunday 21 April 37x
|
01.35 DSSSD bias & leakage current OK - Grafana - attachment 1
FEE64 temperatures OK - attachment 2
|
|
Sun Jun 2 01:45:05 2024, TD, Sunday 2 June 25x
|
02.41 DSSSD bias & leakage current - attachment 1
FEE64 temps OK - attachment 2
|