 Thu May 13 19:52:36 2021, Philippos and Marc, Connection problem 
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At 20:15, We lost connection with AnyDesk.
Liliana restarted Anydesk on the AIDA DAQ PC. All seemed fine on AIDA DAQ but there was a more generic issue on the main DAQ, possibly the timesorter.
Helena restarted all after ~30mn and it's all working again now. |
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Thu May 13 17:05:42 2021, Muneerah, MArc, Thu 13 May 04:00-00:00
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19:08 System Check
Rates from ucesb below 1 kHz
Atachment 1 Stats |
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Thu May 13 07:10:17 2021, CA, TD, May 13th 08:00 - 16:00 shift 34x
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08:10 all system wide checks ok *except*
all FEE64 modules fail ADC calibration
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Thu May 13 00:51:40 2021, Muneerah and OH, Thu 13 May 00:00-08:00 7x
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01:50 Beam on
The leakage current and the voltages been monitered every half an hour and logged in the excel sheet, looks decreasing.
Tempetratures OK
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Wed May 12 18:53:38 2021, JS, Wed 12 20:00-00:00
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19:51 Shift change
Stats ok
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Wed May 12 15:03:10 2021, CB, OH, Wed 12 16:00-20:00 15x
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16:00 Shift change
Statistics OK (attach 1)
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Wed May 12 06:59:55 2021, OH, RDP, Wed 12 May 08:00-16:00
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08:00 While the rates appeared to have quietened around 7am they are back to their previous rate now.
They still seem to be working on the setting. Implant rate in AIDA about 8 per spill. Thick degrader is still in place
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Wed May 12 02:07:59 2021, MA, BA, Wed 12 May 00:00-08:00 9x
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03:12 System Check
attachment 1 : Current
attachment 2 : Temperature |
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Tue May 11 07:21:24 2021, OH, Tuesday 11 May
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08:20 System wide checks all ok except
Base Current Difference
aida01 fault 0xc10c : 0xc10e : 2
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Mon May 10 11:45:15 2021, NH, Confusing behaviour of rates
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Testing the behaviour of powering down the fast ADCs in aida01 (the hot FEE)
Set local control 2 to 0xff in aida01
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Mon May 10 08:49:37 2021, TD, Monday 10 May 21x
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09.51 All system wide checks OK *except*
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Sun May 9 19:29:23 2021, TD, Sunday 9 May 14x
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Sat May 8 09:05:04 2021, TD, Saturday 8 May 27x
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09.54 FEE64 temperatures OK - attachment 1
ADC data item stats OK - attachment 2
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Fri May 7 19:47:54 2021, PJCS, HowTo mitigate excessive temperature in an FEE64
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After tests in the Daresbury T9 system.
Disabling the waveform ADCs in an FEE64 which is running with the FPGA over temperature will drop the FPGA temperature by 10 degrees.
To disable the ADCs open the Local Control browser window and set the ADC Control register , @2, to 0xFF |
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Fri May 7 13:11:22 2021, NH, Friday 7th May
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14:11 - Alpha has been running most of morning
Just saw rates in tape spike to 6 MB/s...
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Thu May 6 16:59:20 2021, TD, OH, Wednesday 6 May 13x
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18.09 NH has installed jumpers LK2-4 for *all* adaptor PCBs
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Wed May 5 20:10:16 2021, OH, Wednesday 5 May Alpha run 12x
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21:10 After all of the works in S4 today the noise in the system was considerably worse
It was decided that before starting a new alpha run a powercycle would be performed.
The powercycle has had no effect on the rates. They are still terrible.
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Wed May 5 16:57:48 2021, TD, Tuesday 5 May
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17.55 Grafana DSSSD bias & leakage current - attachment 1
Note abrupt decrease of DSSSD# 2 leakage current c. 1.5uA at 17.37
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Tue May 4 21:26:43 2021, OH, Alpha run 10x
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22:26 Tape server set up to write to directory May21
DAQ stopped
Slow comparator set to 0x64 for all FEE64 and an ASIC check performed
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Tue May 4 14:26:50 2021, NH, FEE64 Adapter wiring diagram and layout
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A figure showing the FEE64 numbers (a previous diagram had 2/6 and 4/8 on the wrong side of the DSSD) and the wiring of pulser/HV
Also the jumpers connected to the boards
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