 Fri Apr 16 11:42:45 2021, OH, Shifter checklist
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Every 30 minutes:
- Reload statistics (Web browser tab screen 1, workspace 2)
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Fri Apr 16 07:19:00 2021, OH, MA, Friday 16th April 08:00-16:00 14x
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08:19 System wide checks all ok
Baselines reset on WR and FPGA checks for the start of the day
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Fri Apr 16 05:13:09 2021, ML, system wide checks 16x
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system wide checks:
Done around 4am.
################################# |
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Fri Apr 16 02:15:12 2021, NH, Implants/Punchthrough
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Rate with beam < 1000 Hz still
Not Uranium but some fragments possibly produced in the thick 9g degrader
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Fri Apr 16 00:47:36 2021, OH-ML, AIDA DAQ Reset
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1:18 (CET) No rate in AIDA 07.
Oscar did a AIDA DAQ reset and a quick wide check.
(Power cycle |
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Thu Apr 15 22:38:18 2021, OH, Thursday 15th April - 16th April
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23:38 They are testing the finger detector
It is a lot of U they are putting into it which is passing through to AIDA ~3500Hz
Most seems to be punching through
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Thu Apr 15 13:28:07 2021, TD, Thursday 15 April 19x
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13.28 System wide checks
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Thu Apr 15 12:23:22 2021, NH, Fast Discriminator Masks
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It is possible to get good rates with the fast discriminators with a few hot channels mask in aida03 and aida10
Threshold is 0x20 = 3.2 MeV
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Wed Apr 14 15:14:55 2021, PJCS, Note Well
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Please note that for the forseeable future the system function in the menu on the System Wide Checks browser page labelled as
"Collect the Timestamp RAM values" and "Start the Readout Timestamp error tracing"
Are for the use of engineers only unless otherwise instructed. |
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Wed Apr 14 12:14:47 2021, PJCS, Corrections and changes
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14/4/21 @12:00 UK time
Corrected the failure of FADC re-calibration All modules. The problem was a missing > in the .tml file
Edited the sys.tcl file in /MIDAS/TclHttpd/Html/RunControl to comment out where the status of the waveform enable was able to stop the creation |
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Tue Apr 13 16:49:41 2021, TD, Tuesday 13 April 8x
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Rename Options directory
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 Wed Apr 14 09:55:12 2021, TD, Tuesday 13 April
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Two further comments
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Tue Apr 13 14:24:48 2021, TD, S460 information
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aida-gsi Anydesk 897170655
DESPEC remote working - https://sf.gsi.de/d/a4fb2134e06a450ca777/
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Mon Apr 12 18:36:31 2021, NH, [HowTo] AIDA & MBS
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Some instructions on AIDA and MBS and troubleshooting are available here
https://sf.gsi.de/lib/c9ba0b4c-26bc-43d0-9b49-213fc594610f/file/AIDA%20and%20MBS%20Tips%20and%20Troubleshooting.pdf |
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Mon Apr 12 16:49:40 2021, TD, Monday 22 April - pulser walkthrough & alpha background 6x
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16.54 Pulser walkthrough
ASIC settings 2019Dec19-16.19.51
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Sat Apr 10 12:15:54 2021, OH, TD, Saturday 10 April 16x
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12:37 DAQ found crashed. Had crashed at some time following 7:50am following previous statistics update
Unable to recover the FEEs so forced to power cycle
Following power cycle statistics much improved from yesterday.
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Fri Apr 9 16:45:29 2021, NH, HA. GA, GZ, OH, TD, AIDA Noise 6x
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AIDA snout was reconnected and we saw originally a very good reduction in noise from S452 (fig 1)
Occasional bursts of increased rates were noticed, perhaps related to works in S4.
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Fri Apr 9 16:40:36 2021, NH, nnrpi1 Update
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nnrpi1 is now back in S4 with a new SD card and new raspberry pi.
The freezing originally continued (it was the USB system failing) but was fixed with a change to /boot/cmdline.txt coherent_pool=4M
It seems the kernel update to fix one bug introduced another...
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Wed Mar 31 15:46:09 2021, PJCS, HowTo : Synchronize the ASIC clocks.
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To Synchronize the FEE64 ASIC clocks to rise at the same timestamp time use the System function Synchronise the ASIC clocks in the System
Wide Checks browser page.
The Server will read the current timestamp value and calculate, based on the number of FEEs and the access delay, a timestamp value sometime |
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Wed Mar 31 15:40:42 2021, PJCS, Check Options files function added
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There is a new operation available in the System Functions menu in the System Wide Checks page. ( The page needs to be reset once when the FEEs are powered
before this function will appear )
Check the Options files are all the same size |
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Wed Mar 31 12:46:10 2021, PJCS, HowTo : Calibrate the LMK3200 clock devices
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Here is a document showing how and where to calibrate the LMK3200 devices that lock to the system clock and generate the clocks for the ADCs and the
FPGA internal logic. |