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ID |
Date |
Author |
Subject |
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496
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Fri Jun 24 06:56:06 2022 |
OH | Friday 24 June 008:00-16:00 | 07:56 Took over from AM. No issues reported overnight
Stats ok - attachment 1
Temperature ok - attachment 2
Bias and leakage current ok - attachment 3
System wide checks:
Clocks ok
WR
Base Current Difference
aida07 fault 0xc4fe : 0xc53b : 61
aida08 fault 0xf0e9 : 0xf1b7 : 206
White Rabbit error counter test result: Passed 6, Failed 2
FPGA Errors
Base Current Difference
aida07 fault 0x11 : 0x29 : 24
aida08 fault 0x1a : 0x2c : 18
FPGA Timestamp error counter test result: Passed 6, Failed 2
Analysis of R3_359 - attachment 4
Dead time still around 15.9%
Merger item rate around 2E6-4E6
Tape server rate at 7750 kB/s
Current HDD free space 1.7 TB
Time left in HDD 2.59 days
Will run out of space at some point on Sunday
Have started compression of uncompressed raw data on the HDD. Using nice +10
08:45 AIDA07 dropped out from the merger at some point in the preceeding 5-10 minutes. - attachment 5
Am regularly checking the statistics
Was able to stop the DAQ by relaunching the merger.
Reset the FEEs and recovered without a powercylce
Started R4 following this stop
08:58 They have taken the beam to change the ion source for maybe 2 hours
Will stop writing data but continue forwarding to MBS
No storage ticked. Following break will be on R5
11:10 Beam is starting to come back R5 started
Stats ok - attachment 6
Temps ok - attachment 7
Bias and leakage currents ok - attachment 8
13:05 Statistics ok - attachment 9
Temps ok - attachment 10
Bias and leakage curents ok - attachment 11
System wide checks:
WR
Base Current Difference
aida07 fault 0xc53d : 0xc540 : 3
aida08 fault 0xf1be : 0xf1d0 : 18
White Rabbit error counter test result: Passed 6, Failed 2
FPGA
Base Current Difference
aida07 fault 0x2a : 0x2b : 1
FPGA Timestamp error counter test result: Passed 7, Failed 1
Analysis of R5_33 - attachment 12
15:28 Statistics ok - attachment 13
Temperature ok - attachment 14
Bias and leakage current ok - attachment 15
System wide checks:
Base Current Difference
aida07 fault 0xc53d : 0xc546 : 9
aida08 fault 0xf1be : 0xf1e0 : 34
White Rabbit error counter test result: Passed 6, Failed 2
Base Current Difference
aida07 fault 0x2a : 0x2b : 1
FPGA Timestamp error counter test result: Passed 7, Failed 1
Analysis of R5_63 - attachment 16 |
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264
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Fri Apr 23 07:09:57 2021 |
LJW | Friday 23rd April 08:00-12:00 | 08:30
System Checks
Clock Status error:
FEE64 module aida06 global clocks failed, 6
Clock status test result: Passed 11, Failed 1
Understand status as follows
Status bit 3 : firmware PLL that creates clocks from external clock not locked
Status bit 2 : always logic '1'
Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock
Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock
If all these bits are not set then the operation of the firmware is unreliable
ADC Calibration error:
FEE64 module aida06 failed
FEE64 module aida07 failed
FEE64 module aida12 failed
Calibration test result: Passed 9, Failed 3
If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module
White Rabbit Decoder Status error:
Base Current Difference
aida06 fault 0x679f : 0x67a2 : 3
White Rabbit error counter test result: Passed 11, Failed 1
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
FPGA Timestamp error:
Showed larger error message begining 'Got the error Server Internal Error
while trying to obtain /AIDA/Check/Check.tml.'
Statistics - See attacnment 1
Temperatures - See attachment 2
Bias & Leakage Currents - See attachment 3
10:02
System Checks:
Clock Status Error:
FEE64 module aida06 global clocks failed, 6
Clock status test result: Passed 11, Failed 1
Understand status as follows
Status bit 3 : firmware PLL that creates clocks from external clock not locked
Status bit 2 : always logic '1'
Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock
Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock
If all these bits are not set then the operation of the firmware is unreliable
ADC Calibration Error:
FEE64 module aida06 failed
FEE64 module aida07 failed
FEE64 module aida12 failed
Calibration test result: Passed 9, Failed 3
If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module
White Rabbit Decoder Status Error:
Base Current Difference
aida06 fault 0x679f : 0x67a2 : 3
White Rabbit error counter test result: Passed 11, Failed 1
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
FPGA Timestamp error:
Showed larger error message begining 'Got the error Server Internal Error
while trying to obtain /AIDA/Check/Check.tml.'
Statistics - See attacnment 4
Temperatures - See attachment 5
Bias & Leakage Currents - See attachment 6
10:45
System Checks
Clock Status Error:
FEE64 module aida06 global clocks failed, 6
Clock status test result: Passed 11, Failed 1
Understand status as follows
Status bit 3 : firmware PLL that creates clocks from external clock not locked
Status bit 2 : always logic '1'
Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock
Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock
If all these bits are not set then the operation of the firmware is unreliable
ADC Calibration check Error:
FEE64 module aida06 failed
FEE64 module aida07 failed
FEE64 module aida12 failed
Calibration test result: Passed 9, Failed 3
If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module
White Rabbit Decoder Status Error:
Base Current Difference
aida06 fault 0x679f : 0x67a2 : 3
White Rabbit error counter test result: Passed 11, Failed 1
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
FPGA Timestamp error:
Showed larger error message begining 'Got the error Server Internal Error
while trying to obtain /AIDA/Check/Check.tml.'
Statistics - See attacnment 7
Temperatures - See attachment 8
Bias & Leakage Currents - See attachment 9
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263
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Thu Apr 22 23:17:46 2021 |
DJ | Friday 23rd April 00:00-08:00 | Took over from TD ... All is well.
00:45 System Wide Checks
Clock: 12 passed, 0 failed.
ADC Calibration: Passed 12, 0 failed.
White Rabbit Decoder: Passed 4,failed 8. - See screenshot.
FPGA Passed 11, failed 1. - See screenshot.
FEE64 Linux: See screenshot.
-----
02:49 run closed. Checking beam.
03:00 File 55 opened.
03:13:23 DAQ crashed due to AIDA02 rebooting. TD restarted DAQ. Ready at approx 04:00.
File 56 opened at 4:24.
---------
04:30 System Wide Checks (See screenshots)
White Rabbit Decoder: Passed 12, failed 0.
FPGA: page not loading properly.
----
05:37 System wide checks. See screenshots
Clock: Status: 11 passed. 1 fail.
ADC calibration: Passed 9, failed 3.
White Rabbit decoder: Passed 12, failed 0.
-----
07:32 System wide checks (See screenshots).
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268
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Fri Apr 23 20:19:52 2021 |
TD | Friday 23 April 20.00-00.00 |
21.19 system wide checks
FEE64 module aida06 global clocks failed, 6
Clock status test result: Passed 11, Failed 1
Understand status as follows
Status bit 3 : firmware PLL that creates clocks from external clock not locked
Status bit 2 : always logic '1'
Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock
Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock
If all these bits are not set then the operation of the firmware is unreliable
FEE64 module aida06 failed
FEE64 module aida07 failed
FEE64 module aida12 failed
Calibration test result: Passed 9, Failed 3
If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module
Base Current Difference
aida06 fault 0x679f : 0x67a2 : 3
White Rabbit error counter test result: Passed 11, Failed 1
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
Returned 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 23 7 5 7 3 3 2 4 2 3 6 : 36356
aida02 : 67 29 27 4 0 4 2 3 2 3 4 : 28196
aida03 : 14 5 2 4 3 5 2 2 3 3 6 : 36416
aida04 : 5 5 0 7 2 3 3 3 3 3 6 : 36892
aida05 : 26 5 4 3 3 3 1 3 3 3 6 : 36464
aida06 : 20 7 5 2 3 4 2 2 3 3 6 : 36312
aida07 : 24 7 1 2 3 4 2 3 3 3 6 : 36776
aida08 : 22 7 6 2 3 3 1 3 3 3 6 : 36464
aida09 : 20 7 1 2 1 3 3 2 3 3 6 : 36248
aida10 : 9 1 6 1 1 2 2 4 2 3 6 : 35820
aida11 : 15 4 2 3 3 4 3 3 2 3 6 : 35996
aida12 : 22 11 6 2 2 3 2 2 3 3 6 : 36176
Collecting the file size of each FEE64 Options CONTENTS file to check they are all the same
FEE : aida01 => Options file size is 1026 Last changed Fri Apr 23 03:51:08 CEST 2021
FEE : aida02 => Options file size is 1014 Last changed Fri Apr 16 00:56:20 CEST 2021
FEE : aida03 => Options file size is 1014 Last changed Wed Apr 14 21:52:04 CEST 2021
FEE : aida04 => Options file size is 1025 Last changed Sat Apr 17 06:07:36 CEST 2021
FEE : aida05 => Options file size is 1025 Last changed Fri Apr 16 00:53:25 CEST 2021
FEE : aida06 => Options file size is 1014 Last changed Wed Apr 14 21:52:04 CEST 2021
FEE : aida07 => Options file size is 1014 Last changed Wed Apr 14 21:52:04 CEST 2021
FEE : aida08 => Options file size is 1014 Last changed Wed Apr 14 21:52:04 CEST 2021
FEE : aida09 => Options file size is 1014 Last changed Wed Apr 14 21:52:05 CEST 2021
FEE : aida10 => Options file size is 1014 Last changed Wed Apr 14 21:52:06 CEST 2021
FEE : aida11 => Options file size is 1014 Last changed Wed Apr 14 21:52:05 CEST 2021
FEE : aida12 => Options file size is 1025 Last changed Mon Apr 19 09:05:25 CEST 2021
21.20 DSSSD biases & leakage currents OK - attachment 1
FEE64 tempos OK - attachment 2
good event stats - attachment 3
Grafana DSSSD biases & leakage currents for most recent 7 days - attachment 4
23.35 System wide checks - no changes to above
DSSSD biases & leakage currents OK - attachment 5
FEE64 tempos OK - attachment 6
good event stats - attachment 7
23.46 DAQ continues file S460/R51_378 |
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266
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Fri Apr 23 13:13:46 2021 |
MA, TD | Friday 23 April 12.00-16.00 |
14.15 System wide checks
FEE64 module aida06 global clocks failed, 6
Clock status test result: Passed 11, Failed 1
Understand status as follows
Status bit 3 : firmware PLL that creates clocks from external clock not locked
Status bit 2 : always logic '1'
Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock
Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock
If all these bits are not set then the operation of the firmware is unreliable
FEE64 module aida06 failed
FEE64 module aida07 failed
FEE64 module aida12 failed
Calibration test result: Passed 9, Failed 3
If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module
Base Current Difference
aida06 fault 0x679f : 0x67a2 : 3
White Rabbit error counter test result: Passed 11, Failed 1
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
FPGA timestamp errors - reports 'server internal error'
14.16 DSSSD bias & leakage currents OK - attachment 1
FEE64 temps OK - attachment 2
good events stats - attachment 3
14.22 DAQ continues file S460/R51_205
beam intensity 2.2e+09/s
15:53 system check
Rates, Temperatures, Voltages are ok and attached 4,5,6
Clock check
FEE64 module aida06 global clocks failed, 6
Clock status test result: Passed 11, Failed 1
Understand status as follows
Status bit 3 : firmware PLL that creates clocks from external clock not locked
Status bit 2 : always logic '1'
Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock
Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock
If all these bits are not set then the operation of the firmware is unreliable
ADC check
FEE64 module aida06 failed
FEE64 module aida07 failed
FEE64 module aida12 failed
Calibration test result: Passed 9, Failed 3
If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module
White Rabbit
Base Current Difference
aida06 fault 0x679f : 0x67a2 : 3
White Rabbit error counter test result: Passed 11, Failed 1
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
FPGA
Loge page error!
Memory check
Returned 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 23 6 2 1 2 3 2 4 2 3 6 : 36044
aida02 : 15 3 2 2 0 3 2 3 2 3 4 : 27188
aida03 : 29 4 0 3 2 4 2 2 3 3 6 : 36212
aida04 : 4 6 4 4 2 3 3 3 3 3 6 : 36864
aida05 : 19 5 4 2 3 3 1 3 3 3 6 : 36404
aida06 : 24 9 5 2 3 3 3 2 3 3 6 : 36472
aida07 : 20 4 9 0 2 3 2 2 3 3 6 : 36096
aida08 : 22 9 4 3 1 3 1 3 3 3 6 : 36352
aida09 : 20 7 3 2 2 3 3 2 3 3 6 : 36344
aida10 : 25 9 9 5 2 3 2 3 3 3 6 : 36828
aida11 : 24 11 2 0 1 3 1 3 3 3 6 : 36248
aida12 : 26 5 4 2 1 3 2 2 3 3 6 : 36048 |
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549
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Fri Mar 22 08:31:39 2024 |
TD | Friday 22 March |
09.30 Systems check
CAEN N1419ET only channel #0 ON, all other channels off
DSSSD bias -120V leakage current -5.500uA - attachment 1
Leakage current of 5.5uA corresponds to c. 3nA/cm2/100um indicating high quality device ( assuming ambient temperature c. 21 deg C )
FEE64 temperatures OK *except* aida02 ASIC temperature - attachment 2
N.B. aida02 ASIC temperature sensor faulty - reading > 500 deg C - probably poor connection FEE64-ASIC mezzanine
All system wide checks OK *except*
aida04 WR decoder status 0x10 - attachment 3
WR timestamps OK - attachment 4
09.42 NH reports "195au implanting in aida, Ca 100 per spill"
ASIC settings
LEC/MEC slow comparator 0x64, LEC/MEC fast comparator 0xff, HEC comarator 0x2
aida02 and aida04 negative input polarity ( n+n Ohmic strips ), all other FEE64s positive input polarity
09.46 all histograms and stats zero'd
ADC, DISC, PAUSE, RESUME & Correlation Scaler data items stats - attachments 5-9
per FEE64 1.8.W spectra - 20us FSR - attachments 10-11
aida08 noise significantly lower than all other FEE64s
per FEE64 1.8.H spectra - attachments 12-13
data suggests 195Au ions are focussed on central Si wafer, ion energies to c. 5GeV, no evidence lower A/Z ( fission ) ions with lower energy loss
per FEE64 1.8.L spectra - attachments 14-15
per FEE64 Rate Stat spectra - attachments 16-19
Merger, TapeServer - attachments 20-21
Merger idle !?
Tape Server no storage mode but forwarding data at c. 1Mb/s
data file R31
13.30 NH reports "beam over"
DSSSD bias -120V leakage current -6.500uA - attachment 22
FEE64 temperatures OK *except* aida02 ASIC temperature - attachment 23
N.B. aida02 ASIC temperature sensor faulty - reading > 500 deg C - probably poor connection FEE64-ASIC mezzanine
All system wide checks OK *except*
aida05 & aida07 FPGA timestamp errors - attachment 24
aida04 WR decoder status 0x10 - attachment 25
WR timestamps OK - attachment 26
ADC data items stats - attachments 27
per FEE64 Rate spectra - attachments 28-29
per FEE64 1.8.L spectra - attachments 30-31
per FEE64 1.8.H spectra - attachments 32-33
per FEE64 1.8.W spectra - 20us FSR - attachments 34-35
Merger, TapeServer - attachments 36-37
Merger idle !?
Tape Server no storage mode but forwarding data at c. 1Mb/s
data file R31
20:30 AIDA Powered down
DSSSD remains biased at -120V, monitor the current over the weekend (Grafana)
Merger still showing idle... "no data to storage" makes xfer Links disappear?
Tape server stopped
11.20 Saturday 23 March
Grafana DSSSD bias/leakage current monitor screenshot - attachment 38
https://despec-vm-01.gsi.de/grafana/d/6SAfgl0Mz/aida?orgId=1&refresh=1m&from=now-2d&to=now
DSSSD#1 leakage current recovered to c. pre-beam values
08.05 Monday 25 March
Grafana DSSSD bias/leakage current monitor screenshot - attachment 39 |
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342
|
Fri May 21 15:03:48 2021 |
CA | Friday 21st May 16:00 - 00:00 shift | 16:00 CA takes over
DSSD1 n+n sides 0x20 on ASICs 1-3 and 0x64 on ASIC 4
DSSD2 n+n sides 0x1b on ASICs 1-3 and 0x64 on ASIC 4
PULSER SETTINGS
---------------------------
Pulse is ON
Positive Tail Pulse
Trigger Source is Internal Clock
Trigger Threshold is 3.5
Amplitude : 2.0 Volts
Rep Rate : 2.0 hZ
Delay : 250.0 ns
Fall Time : 1 ms
Attenuation : 1
Display is : Volts
Equivalent keV is : 200.0
Ramp Start at 0.01 Volts
Ramp Stop at 9.99 Volts
Ramp Start at 1.0 keV
Ramp Stop at 999.0 keV
Ramp Time is 60 seconds
# Ramp Cycles is 1
16:14 system wide checks all ok *except*
Base Current Difference
aida05 fault 0x500 : 0x570 : 112
White Rabbit error counter test result: Passed 15, Failed 1
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
16:17 temperatures ok - attachment 1
statistics ok - attachment 2
detector bias / leakage currents ok - attachment 3
analysis of R14_1625 - FEE7 deadtime at 4.5%
18:06 system wide checks all ok *except*
Base Current Difference
aida05 fault 0x500 : 0x571 : 113
White Rabbit error counter test result: Passed 15, Failed 1
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
18:07 temperatures ok - attachment 4
statistics ok - attachment 5
detector bias / leakage currents ok - attachment 6
analysis of R14_1662 - FEE7 deadtime at 4.3%
19:07 DAQ continues ok - writing to file R14_1682
20:07 system wide checks all ok *except*
Base Current Difference
aida05 fault 0x500 : 0x572 : 114
White Rabbit error counter test result: Passed 15, Failed 1
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
20:10 temperatures ok - attachment 7
statistics ok - attachment 8
detector bias / leakage currents ok - attachment 9
analysis of R14_1703 - max deadtime at 4.0% - attachment 10
20:35 rate spectra - attachment 11
HEC spectra - attachment 12 & 13
20:36 all histograms zeroed
20:37 DAQ continues ok - writing to file R14_1712
20:45 /media/1e121361-83d3-4825-b6ae-9700b07e0ca7 at 94% use.
~ 12 hours until 100% at 10 MB/s data rate, not accounting for compression of older files
21:12 no beam - writing to file R14_1723
21:17 beam is back
22:07 system wide checks all ok - WR decoder fault same as entry at 20:07
22:08 temperatures ok - attachment 14
statistics ok - attachment 15
detector bias / leakage currents ok - attachment 16
analysis of R14_1740 - max deadtime at 4.2% - attachment 17
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341
|
Fri May 21 07:03:50 2021 |
OH, TD | Friday 21 May 08:00-16:00 | 08:00 OH and TD take over
Current settings p+n sides at 0xc
DSSD1 n+n sides 0x20 on ASICs 1-3 and 0x64 on ASIC 4
DSSD2 n+n sides 0x1b on ASICs 1-3 and 0x64 on ASIC 4
PULSER SETTINGS
---------------------------
Pulse is ON
Positive Tail Pulse
Trigger Source is Internal Clock
Trigger Threshold is 3.5
Amplitude : 2.0 Volts
Rep Rate : 2.0 hZ
Delay : 250.0 ns
Fall Time : 1 ms
Attenuation : 1
Display is : Volts
Equivalent keV is : 200.0
Ramp Start at 0.01 Volts
Ramp Stop at 9.99 Volts
Ramp Start at 1.0 keV
Ramp Stop at 999.0 keV
Ramp Time is 60 seconds
# Ramp Cycles is 1
08:29 System wide checks ok - WR difference at 111
Statistics ok (Still high following the sharp rise at 18:30 yesterday) - attachment 1
Temperature ok - attachment 2
Bias and leakage current ok - attachment 3
09:58 System wide checks ok - WR difference at 111
Statistics ok - attachment 4
Temperature ok - attachment 5
Bias and leakage current ok - attachment 6
Max deadtime this morning has been around 5.5% on FEE8
12:32 System wide checks ok - WR difference at 111
Statistics ok - attachment 7
Temperature ok - attachment 9
Bias and leakage current ok - attachment 8 |
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130
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Fri Feb 21 09:39:38 2020 |
TD, NH | Friday 21 February |
Attachment 1 - layout 2 - stat spectra
Attachment 2 - detector biases & leakage currents - OK
Attachment 3 - FEE64 temperatures - OK
Attachments 4-7 - TapeServer, Merger, Merger Statistics, good event statistics - OK
10:40 ASIC check load x2
13.12 DAQ stopped c. 10.50
unable to connect messages for multiple FEE64s
After lunch powwer-cycled FEE64s and restarted DAQ
aida03 crashed (see https://elog.ph.ed.ac.uk/DESPEC/131 ) and rebooted by issuing reboot command as root
Data file 20FEB20/R1
ASIC settings 2019Oct31-13.24.23
slow comparator 0xa -> 0x64
BNC PB-5 pulser OFF
continue alpha background run |
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468
|
Fri May 20 16:22:01 2022 |
TD | Friday 20 May | 17.20 DAQ stopped
Attachment 1 - DSSSD bias & leakage current
Attachment 2 - grafana DSSSD bias, leakage current & temp - OK
Attachment 3 - FEE64 temps - OK |
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119
|
Fri Dec 20 12:04:03 2019 |
NH, TD | Friday 20 December 2019 | Fig 1: DSSD Leakage currents ok
Fig 2: FEE Temps ok
Fig 3: aida08 has a few timestamp errors in merger
Fig 4, 5: GSI WR OK
Fig 6: All System wide checks passed
FIg 7: Stats good
13:11 - Alpha Run Stopped, Final File: R9_6
FEEs powered off, DSSD bias off. |
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80
|
Fri Nov 1 10:46:13 2019 |
CA, TD, NH | Friday 1st November 2019 | 11.46 - attachments 1,2,3: bias/leakage currents, good event statistics and fee temperatures (respectively)
before removing aluminium foil upstream of AIDA
note - slow comparator threshold 0x64 (alpha background), LEC fast comparator threshold 0xff, pulser OFF
11.52 - attachments 4,5,6: bias/leakage currents, good event statistics and fee temperatures (respectively)
after removing aluminium foil upstream of AIDA
- base of AIDA snout has Mylar shielding |
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205
|
Fri Mar 19 17:16:45 2021 |
TD | Friday 19 March |
Screenshots of successive displays of Options for FEE64s aida01, 02, 03 and 04. |
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580
|
Fri Apr 19 13:52:34 2024 |
JB, CC, TD | Friday 19 April contd. |
12.00 Replaced AIDA ASIC mezzanine of aida01 to fix issue with asic #3
During replacement the HDMI connector of the adjacent FEE64 aida09 became disconnected from the FEE64 PCB
aida09 ( MAC ee:10 ) replaced (MAC 41:cf:ad )
AIDA FEE64 adaptor PCBs for aida01, aida14 and aida09 disconnected and re-connected during this process
DSSSD bias & leakage current OK - attachment 1
FEE64 temps OK - attachment 2
*except* aida02 ASIC temp - known fault
System wide checks OK *except* WR/FPGA errors - attachments 3-4
WR timestamps OK - attachment 5
ADC, DISC, PAUSE, RESUME and correlation data stats - attachments 6-10
ADC data items 10/16 < 20k, max 143k
per FEE64 Rate spectra - attachment 11
per FEE64 1.8.W spectra - 20us FSR - attachments 12-13
15.10 Synchronise ASIC clocks
Re-calibrate ALL ADCs
ASIC settings 2024Mar27-11.25.32
Changes ( https://elog.ph.ed.ac.uk/CARME/499 )
IBias LF feedback from 0xf to 0x8
Diode link threshold from 0xbf to 0xca
New ASIC settings saved as 2024Apr19-15.22.49
All FEE64 slow comparators -> 0x14
Data file S100_alpha/R12
Pulser ealkthrough (test +)
BNC PB-5 settings
Amplitude 10.0-1.0V @ 1.0V step
Attenuation x10
Frequency 25Hz
Polarity +
Tail pulse
tau_d 1ms
16.35 DAQ ends OK file S100_alpha/R12_24
per p+n FEE64 1.8.L spectra - attachment 14
aida09 pulser peak width 54 ch FWHM
17.38 Data file S100_alpha/R13
Pulser walkthrough (test -)
BNC PB-5 settings
Amplitude 10.0-1.0V @ 1.0V step
Attenuation x10
Frequency 25Hz
Polarity -
Tail pulse
tau_d 1ms
18.43 DAQ ends OK file S100_alpha/R13_20
per p+n FEE64 1.8.L spectra - attachment 15
18.55 Current status
FEE64 power ON
DSSSD bias ON
All FEE64 slow comparator 0x14
DAQ going -> Merger -> TapeServer (no storage mode) -> MBS ( but data stream not yet being read by MBS )
To Do
- S4 currently closed/controlled access for FRS startup
If we have access to S4 tomorrow
- switch test - to test + ( not critical )
- test AIDA interlock
- further alpha background?
22.47 DSSSD bias & leakage current OK - attachments 16-17
FEE64 temps OK - attachment 18
*except* aida02 ASIC temp - known fault
ADC data item stats - attachment 19
per FEE64 Rate spectra - attachment 20
Data link, Tape Server & Merger - attachments 21-23
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579
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Fri Apr 19 02:35:14 2024 |
TD | Friday 19 April |
03.30
09.10
09.25 data file S100_alpha/R11
BNC PB-5 pulser data
amplitude 10.0V
attenuation x10
tau_d = 1ms
polarity - ( initially + )
frequency 25Hz
ASIC settings2024Mar27-11.25.32
slow comparator 0x64 all FEE64s
aida02 pulser peak width 129 ch FWHM
polsrity +
aida09 pulser peak width 57 ch FWHM
09.40 switch to no storage
p+n FEE64 slow comparators 0x64 -> 0xa
n+n FEE64 slow comparators 0x64 -> 0xf
radioactive source 152Eu 370kBq installed on the bottom side of the snout, centred tranversely, located beneath bplas-DSSSD-DSSSD-bplas position.
ADC data item stats - attachment 35
9/16 < 20k, max 108k
per FEE64 Rate spectra - attachment 36
10.44 152Eu source removed
ADC data item stats - attachment 37
9/16 < 20k, max 102k
per FEE64 Rate spectra - attachment 38 |
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482
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Sat Jun 18 09:46:57 2022 |
OH, NH | Friday 17th June | Summary of the day:
Small improvements were made throughout the day but by far the biggest change to the rate in the FEEs came from disabling the waveforms
This was done by setting ADC con
Initial jumper configuration:
FEE LK
1 2 4
2 1 2 4
3 2 3 4
4 2 4
5 2 4
6 1 2 4
7 2 3 4
8 1 2 4
13:22 LK2, 3 and 4 on all p+n - attachment 1
14:20 AC mains relay connected to AC voltage stabilisers + on separate mains socket from DESPEC - attachment 2
Same configuration but waveforms disabled (p+n improvment) - attachment 3
Layout 1 - attachment 4
14:32 all FEE power cables moved to PSU 2 (Lower one in rack, upper one was slow to start for 1 FEE pair, likely the 5V slow to start)
Previously all FEEs on their own pair within a psu
New order 1,3 2,4 5,7 6,8
Waveforms on - all bad - attachment 5
Waveforms off - all p+n better - attachment 6
14:54 interlock removed from AC mains relay
Also noticed adaptor board on 2 not in fully -> Now in
p+n generally better - attachment 7
Without waveforms - p+n better again - attachment 8
16:04 Platform moved into position
Interlock power cable removed from extension lead
w/ waveform - p+n slightly worse
w/o waveform - p+n same as beffore
16:14 LK3 removed from 1 and 5
w/ waveform -> p+n slightly worse - attachment 9
w/o waveform -> p+n best yet - attachment 10
16:33 LK1 wasn't on all n+n was only on 2, 6 and 8
Removed from 6 -> only one LK1 per DSSD
w/ waveforms - all bad - attachment 11
w/o waveforms - no change - attachment 12
16:59 LK1 removed from 2->4 This is the FEE with the BIAS braid
w/ waveform p+n better - attachment 13
w/0 waveform p+n better, n+n worse? - attachment 14
17:21 Bias filters added to n+n
w/ waveform - no change - attachment 15
w/o wwaveofrm - P=n worse - attachment 16
Stats 0x21 - attachment 17
Stats 0x14 - attachment 18
Stats 0x12 - attachment 19
17:42 Bias filter removed and bias floated (LK1 removed)
w/ waveform all worse - attachment 20
w/o waveform -> p+n worse, n+n similar
18:29 LK1 back on 4+8
w/ waveform -> poor
w/0 waveform - recovered previous - attachment 20
18:32 LK 2 and 4 removed from 2 +6
Also noticed ground lemo on aida02 not fully inserted which has been corrected
w/ waveform poor - attachment 21
Threshold 0xF - attachment 22
w/o waveform - attachment 23 |
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229
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Fri Apr 16 07:19:00 2021 |
OH, MA | Friday 16th April 08:00-16:00 | 08:19 System wide checks all ok
Baselines reset on WR and FPGA checks for the start of the day
Statistics ok - attachment 1
Temperatures ok - attachment 2
Bias and leakage currents ok - attachment 3
09:03 During the reset last night I repaired the OptionsDB for aida02 from the Options.Pristine directory.
No corruptions have been noted since
10:10 System check, clcock and ADC ok
Base Current Difference
aida07 fault 0xfb3a : 0xfb3d : 3
White Rabbit error counter test result: Passed 11, Failed 1
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
FPGA and memory check ok
Statistics ok - attachment 4
Temperatures ok - attachment 5
Bias and leakage currents ok - attachment 6
10:39 Fission fragments were punching through AIDA
This was even with the maxmimum degraders in place
They are now placing a thick plate in front of AIDA to block the fragments while they beam tune.
11:38 They have found the issue with the degrader and have corrected it.
We now see next to no implants in AIDA as expect.
Histograms reset at around 11:35
Layout 2 shows very few implants in 5 minutes - attachment 7
12:08 The high implantation rates of ions into AIDA is clearly seen in the large transients on the leakage currents - attachment 8
This was a large amount of dose going into the detectors which we should try to avoid
13:25 system check, clock and ADC ok
Base Current Difference
aida05 fault 0xc879 : 0xc87b : 2
aida06 fault 0x323c : 0x323e : 2
aida07 fault 0xfb3a : 0xfb3f : 5
aida08 fault 0xd3d6 : 0xd3d8 : 2
White Rabbit error counter test result: Passed 8, Failed 4
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
Statistics ok - attachment 9
Temperatures ok - attachment 10
Bias and leakage currents ok - attachment 11
FPGA and memory check ok
16:10 system check, clock and ADC ok
Base Current Difference
aida05 fault 0xc879 : 0xc87b : 2
aida06 fault 0x323c : 0x323e : 2
aida07 fault 0xfb3a : 0xfb3f : 5
aida08 fault 0xd3d6 : 0xd3d8 : 2
White Rabbit error counter test result: Passed 8, Failed 4
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
Statistics ok - attachment 12
Temperatures ok - attachment 13
Bias and leakage currents ok - attachment 14
FPGA and memory check ok |
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319
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Fri May 14 19:01:09 2021 |
JS | Friday 14th May 20:00-00:00 | 20:00 Taking over from CB
20:33 Doing full checks.
Temps ok elog:319/8
Bias ok elog:319/1
Clock check - ok
ADC Calc check - ok
White Rabbit -
Base Current Difference
aida01 fault 0xf932 : 0xf934 : 2
aida02 fault 0x62ec : 0x62ee : 2
aida03 fault 0x8679 : 0x867b : 2
aida04 fault 0xf0e4 : 0xf0e6 : 2
aida05 fault 0x9db8 : 0x9dc5 : 13
aida06 fault 0x7f18 : 0x7f1a : 2
aida07 fault 0xdd2c : 0xdd2e : 2
aida08 fault 0x1557 : 0x1559 : 2
White Rabbit error counter test result: Passed 8, Failed 8
FPGA Timestamp errors -
Base Current Difference
aida05 fault 0x0 : 0x3 : 3
FPGA Timestamp error counter test result: Passed 15, Failed 1
Memory Info-
Returned 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 35 34 30 8 1 4 1 2 2 3 6 : 35772
aida02 : 37 30 28 5 3 1 2 4 2 3 6 : 36644
aida03 : 41 29 30 16 4 3 1 5 1 3 6 : 36588
aida04 : 13 6 23 12 4 4 4 4 2 2 6 : 35412
aida05 : 20 32 23 10 2 2 2 2 1 4 6 : 36736
aida06 : 14 5 10 5 1 3 2 3 2 3 6 : 35680
aida07 : 44 23 22 9 4 3 1 3 2 3 6 : 36200
aida08 : 39 30 28 9 0 3 2 3 3 2 6 : 35308
aida09 : 41 31 28 10 2 5 1 3 1 3 6 : 35484
aida10 : 43 23 27 7 3 1 1 3 3 3 6 : 36916
aida11 : 39 35 17 10 3 3 2 2 2 3 6 : 35908
aida12 : 37 36 15 10 2 2 2 4 3 2 6 : 35684
aida13 : 47 32 17 7 4 2 3 4 3 2 6 : 36012
aida14 : 23 33 14 10 3 4 3 4 3 2 6 : 36164
aida15 : 44 28 24 12 3 2 4 3 3 2 6 : 35920
aida16 : 22 17 24 17 3 4 2 3 1 3 6 : 35648
Stats
Aida Correlation Info #8 - elog:319/2 same as elog:317/27
Resume info #3 - elog:319/3 same as elog:317/26
Pause info #2 - elog:319/4 same as elog:317/32
AIDA disk info #6 - elog:319/5 same as elog:317/31
AIDA ADC data items - elog:319/6 same as elog:317/30
Good Events - elog:319/7 same as elog:317/29
[I had some artifacts in AnyDesk when looking at the stats pages with many zeros, but could see
clearly once uploaded the screenshots]
Analysis R5_108 elog:319/9
Pause 149 Resume 150
Highest deadtime FEE10 3%
21:01
ucesb ok - Max 1700 Hz Implant - 1MHz Decay
21:35
Temps ok
Bias ok
Clock check - ok
ADC Calc check - ok
White Rabbit -
Base Current Difference
aida01 fault 0xf932 : 0xf934 : 2
aida02 fault 0x62ec : 0x62ee : 2
aida03 fault 0x8679 : 0x867b : 2
aida04 fault 0xf0e4 : 0xf0e6 : 2
aida05 fault 0x9db8 : 0x9dc5 : 13
aida06 fault 0x7f18 : 0x7f1a : 2
aida07 fault 0xdd2c : 0xdd2e : 2
aida08 fault 0x1557 : 0x1559 : 2
White Rabbit error counter test result: Passed 8, Failed 8
Base Current Difference
aida05 fault 0x0 : 0x3 : 3
FPGA Timestamp error counter test result: Passed 15, Failed 1
Returned 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 39 34 29 8 1 4 1 2 2 3 6 : 35772
aida02 : 46 29 28 5 3 2 2 3 2 3 6 : 36288
aida03 : 39 25 29 16 4 2 2 5 1 3 6 : 36660
aida04 : 14 6 19 12 4 4 3 4 2 2 6 : 35096
aida05 : 20 30 24 10 2 2 2 2 1 4 6 : 36736
aida06 : 26 4 11 5 2 4 3 2 2 3 6 : 35672
aida07 : 46 22 22 9 4 3 1 3 2 3 6 : 36200
aida08 : 28 32 28 9 0 2 2 4 3 2 6 : 35664
aida09 : 32 30 29 10 3 5 2 3 1 3 6 : 35776
aida10 : 39 23 25 7 3 1 1 3 3 3 6 : 36868
aida11 : 40 31 21 10 3 3 1 4 1 3 6 : 35688
aida12 : 17 31 12 10 2 2 3 4 3 2 6 : 35772
aida13 : 35 28 22 7 4 2 3 4 3 2 6 : 36012
aida14 : 30 33 14 10 3 4 3 4 3 2 6 : 36192
aida15 : 34 26 24 12 3 2 4 3 3 2 6 : 35864
aida16 : 38 24 27 17 3 4 2 3 1 3 6 : 35816
Stats
Good Events - elog:319/10
AIDA ADC data items - elog:319/11
AIDA disk info #6 - elog:319/12
Pause info #2 - elog:319/13
Resume info #3 - elog:319/14
Aida Correlation Info #8 - elog:319/15 - rates showed zero, checked again and normal elog:319/17
Analysis R5_128 elog:319/16
Pause 167 Resume 166
Highest deadtime FEE10 5%
22:00
Temps ok
Stats ok
ucesb ok
22:35
Temps ok
Stats ok
ucesb- DSSD 2 is reading consistently 30% lower, not sure if this is dead time issue cropping up
again elog:319/17
22:54 They are closing the file, we are on R5_155
23:00 |
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317
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Fri May 14 14:57:32 2021 |
CB + OH, TD, NH | Friday 14th May 16:00-20:00 | 16:00 Shift taken over from CA
16:00
Temperatures OK. Attach 1.
Upon reloading aida11 first returns "No respose" for all values.
Upon refreshing, aida11 responds but aida 9 returns "No response".
Upon refreshing again, attach 1.
Bias OK. Attach 2.
Statistics OK. Attach 3-7
System-wide checks
Clock OK
ADC - all fail
Base Current Difference
aida01 fault 0xf932 : 0xf933 : 1
aida02 fault 0x62ec : 0x62ed : 1
aida03 fault 0x8679 : 0x867a : 1
aida04 fault 0xf0e4 : 0xf0e5 : 1
aida05 fault 0x9db8 : 0x9dc3 : 11
aida06 fault 0x7f18 : 0x7f19 : 1
aida07 fault 0xdd2c : 0xdd2d : 1
aida08 fault 0x1557 : 0x1558 : 1
White Rabbit error counter test result: Passed 8, Failed 8
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
Base Current Difference
aida05 fault 0x0 : 0x3 : 3
FPGA Timestamp error counter test result: Passed 15, Failed 1
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
Returned 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 32 28 25 7 1 4 1 3 2 3 6 : 36112
aida02 : 43 28 29 5 4 2 3 4 1 3 6 : 36092
aida03 : 39 26 28 5 4 3 2 5 1 3 6 : 36428
aida04 : 9 5 21 8 5 4 4 4 2 2 6 : 35292
aida05 : 46 32 26 7 2 2 2 2 2 3 6 : 35768
aida06 : 4 5 16 1 3 4 2 4 1 3 6 : 35352
aida07 : 47 21 25 5 4 3 1 4 1 3 6 : 35604
aida08 : 62 33 32 6 0 2 3 3 3 2 6 : 35520
aida09 : 33 25 28 7 3 5 2 4 1 3 6 : 36140
aida10 : 47 29 22 6 3 2 2 2 2 3 6 : 35716
aida11 : 39 30 29 6 2 3 1 3 2 3 6 : 36124
aida12 : 38 36 20 6 3 2 3 3 3 2 6 : 35448
aida13 : 42 29 24 3 4 2 3 3 3 2 6 : 35440
aida14 : 31 28 18 7 3 3 4 4 2 2 6 : 35228
aida15 : 48 25 30 5 3 2 4 4 2 2 6 : 35272
aida16 : 37 16 28 6 3 3 2 2 2 3 6 : 35796
Collecting the file size of each FEE64 Options CONTENTS file to check they are all the same
FEE : aida01 => Options file size is 1026 Last changed Thu May 13 05:49:42 CEST 2021
FEE : aida02 => Options file size is 1014 Last changed Thu Apr 29 14:43:46 CEST 2021
FEE : aida03 => Options file size is 1014 Last changed Thu Apr 29 14:43:50 CEST 2021
FEE : aida04 => Options file size is 1014 Last changed Thu Apr 29 14:43:53 CEST 2021
FEE : aida05 => Options file size is 1014 Last changed Thu Apr 29 14:43:55 CEST 2021
FEE : aida06 => Options file size is 1014 Last changed Thu Apr 29 14:43:59 CEST 2021
FEE : aida07 => Options file size is 1014 Last changed Thu Apr 29 14:44:02 CEST 2021
FEE : aida08 => Options file size is 1025 Last changed Wed May 05 12:15:54 CEST 2021
FEE : aida09 => Options file size is 1014 Last changed Thu Apr 29 14:44:08 CEST 2021
FEE : aida10 => Options file size is 1014 Last changed Thu Apr 29 14:44:57 CEST 2021
FEE : aida11 => Options file size is 1014 Last changed Thu Apr 29 14:44:57 CEST 2021
FEE : aida12 => Options file size is 1014 Last changed Thu Apr 29 14:44:57 CEST 2021
FEE : aida13 => Options file size is 1025 Last changed Fri May 07 19:40:34 CEST 2021
FEE : aida14 => Options file size is 1014 Last changed Thu Apr 29 14:44:57 CEST 2021
FEE : aida15 => Options file size is 1014 Last changed Thu Apr 29 14:44:57 CEST 2021
FEE : aida16 => Options file size is 1014 Last changed Thu Apr 29 14:44:57 CEST 2021
16:15 Control handed over to OH temporarily.
16:25 AIDA stopped. OH attempts to update Merger. Discriminators off.
16:29 AIDA restart begins.
16:33 AIDA restarted.
16:40 Dead time still very high ~50% in most FEEs.
16:50 Checking effect of threshold on dead time.
16:53 Checking waveform effect on deadtime. DAQ stopped. Turning waveforms on, threshold increased to max. This
*reduces* deadtime to <10%.
Sampling ADCs were disabled (switched off) late Wednesday evening.
17:01 DAQ can be restarted.
17:27 Finished checking effect of threshold on dead time. 120 keV front. 320 keV back.
17:33 Analysis of R5_45 - x strips 0xc - y strips 0x20
17:40 OH hands back control.
Temperature OK - attach 10
Bias OK - attach 11
Stats - attach 12-17
System-wide checks
Clock - all pass
ADC - all pass
WR
Base Current Difference
aida01 fault 0xf932 : 0xf933 : 1
aida02 fault 0x62ec : 0x62ed : 1
aida03 fault 0x8679 : 0x867a : 1
aida04 fault 0xf0e4 : 0xf0e5 : 1
aida05 fault 0x9db8 : 0x9dc3 : 11
aida06 fault 0x7f18 : 0x7f19 : 1
aida07 fault 0xdd2c : 0xdd2d : 1
aida08 fault 0x1557 : 0x1558 : 1
White Rabbit error counter test result: Passed 8, Failed 8
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
Base Current Difference
aida05 fault 0x0 : 0x3 : 3
FPGA Timestamp error counter test result: Passed 15, Failed 1
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
Returned 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 56 35 27 8 1 4 1 2 2 3 6 : 35816
aida02 : 43 31 27 5 3 1 3 3 2 3 6 : 36404
aida03 : 45 28 28 16 4 2 2 4 1 3 6 : 36180
aida04 : 2 2 18 12 4 3 3 4 2 2 6 : 34872
aida05 : 28 28 24 10 2 2 2 2 1 4 6 : 36752
aida06 : 28 11 9 5 2 3 3 3 1 3 6 : 35064
aida07 : 52 24 23 9 4 3 1 2 2 3 6 : 35744
aida08 : 21 26 27 8 0 2 3 3 3 2 6 : 35284
aida09 : 40 32 26 10 3 5 1 3 1 3 6 : 35520
aida10 : 46 23 27 7 3 1 1 3 3 3 6 : 36928
aida11 : 49 31 20 10 2 2 1 2 2 3 6 : 35516
aida12 : 39 35 17 9 2 2 3 4 3 2 6 : 35940
aida13 : 40 32 20 7 4 2 3 4 3 2 6 : 36032
aida14 : 33 33 16 10 3 4 3 4 3 2 6 : 36236
aida15 : 53 27 25 12 3 2 4 4 2 2 6 : 35452
aida16 : 35 22 32 15 3 4 3 3 1 3 6 : 36060
Collecting the file size of each FEE64 Options CONTENTS file to check they are all the same
FEE : aida01 => Options file size is 1026 Last changed Thu May 13 05:49:42 CEST 2021
FEE : aida02 => Options file size is 1014 Last changed Thu Apr 29 14:43:46 CEST 2021
FEE : aida03 => Options file size is 1014 Last changed Thu Apr 29 14:43:50 CEST 2021
FEE : aida04 => Options file size is 1025 Last changed Fri May 14 16:54:56 CEST 2021
FEE : aida05 => Options file size is 1014 Last changed Thu Apr 29 14:43:55 CEST 2021
FEE : aida06 => Options file size is 1014 Last changed Thu Apr 29 14:43:59 CEST 2021
FEE : aida07 => Options file size is 1014 Last changed Thu Apr 29 14:44:02 CEST 2021
FEE : aida08 => Options file size is 1025 Last changed Wed May 05 12:15:54 CEST 2021
FEE : aida09 => Options file size is 1014 Last changed Thu Apr 29 14:44:08 CEST 2021
FEE : aida10 => Options file size is 1014 Last changed Thu Apr 29 14:44:57 CEST 2021
FEE : aida11 => Options file size is 1014 Last changed Thu Apr 29 14:44:57 CEST 2021
FEE : aida12 => Options file size is 1014 Last changed Thu Apr 29 14:44:57 CEST 2021
FEE : aida13 => Options file size is 1025 Last changed Fri May 07 19:40:34 CEST 2021
FEE : aida14 => Options file size is 1014 Last changed Thu Apr 29 14:44:57 CEST 2021
FEE : aida15 => Options file size is 1014 Last changed Thu Apr 29 14:44:57 CEST 2021
FEE : aida16 => Options file size is 1014 Last changed Thu Apr 29 14:44:57 CEST 2021
18:30
Temperatures - OK (attach 18)
Bias OK (attach 19)
Stats - attach 20-24
System-wide checks
Clock - all pass
ADC - all pass
Base Current Difference
aida01 fault 0xf932 : 0xf933 : 1
aida02 fault 0x62ec : 0x62ed : 1
aida03 fault 0x8679 : 0x867a : 1
aida04 fault 0xf0e4 : 0xf0e5 : 1
aida05 fault 0x9db8 : 0x9dc3 : 11
aida06 fault 0x7f18 : 0x7f19 : 1
aida07 fault 0xdd2c : 0xdd2d : 1
aida08 fault 0x1557 : 0x1558 : 1
White Rabbit error counter test result: Passed 8, Failed 8
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
Base Current Difference
aida05 fault 0x0 : 0x3 : 3
FPGA Timestamp error counter test result: Passed 15, Failed 1
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
Returned 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 41 31 31 8 1 4 1 2 2 3 6 : 35788
aida02 : 42 31 29 5 3 2 4 4 1 3 6 : 36304
aida03 : 29 30 29 16 4 3 2 4 1 3 6 : 36276
aida04 : 28 4 20 12 4 3 4 4 2 2 6 : 35280
aida05 : 25 28 23 10 2 2 2 2 1 4 6 : 36724
aida06 : 5 3 10 5 2 4 2 2 2 3 6 : 35308
aida07 : 38 26 22 9 4 3 1 2 2 3 6 : 35688
aida08 : 52 30 28 8 0 2 2 3 3 2 6 : 35200
aida09 : 22 26 21 10 3 4 1 4 1 3 6 : 35704
aida10 : 37 28 25 7 3 1 1 3 3 3 6 : 36900
aida11 : 53 30 20 10 2 3 2 2 2 3 6 : 35908
aida12 : 37 34 17 10 2 2 3 4 3 2 6 : 35956
aida13 : 47 34 16 7 4 2 3 4 3 2 6 : 36012
aida14 : 37 29 17 10 3 4 3 4 3 2 6 : 36236
aida15 : 44 28 25 12 3 2 4 4 2 2 6 : 35424
aida16 : 40 21 33 15 3 4 1 3 1 3 6 : 35576
18:40 Analysed R5_67. Attached. Dead time improved. Max ~1.5%
19:40 Temperatures OK
Bias OK - attach 26
Stats - attach 27-32
System-wide checks
Clock, ADC - all pass
WR
Base Current Difference
aida01 fault 0xf932 : 0xf934 : 2
aida02 fault 0x62ec : 0x62ee : 2
aida03 fault 0x8679 : 0x867b : 2
aida04 fault 0xf0e4 : 0xf0e6 : 2
aida05 fault 0x9db8 : 0x9dc4 : 12
aida06 fault 0x7f18 : 0x7f1a : 2
aida07 fault 0xdd2c : 0xdd2e : 2
aida08 fault 0x1557 : 0x1559 : 2
White Rabbit error counter test result: Passed 8, Failed 8
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
Base Current Difference
aida05 fault 0x0 : 0x3 : 3
FPGA Timestamp error counter test result: Passed 15, Failed 1
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
Returned 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 41 33 30 8 1 4 1 2 2 3 6 : 35788
aida02 : 51 30 30 5 3 2 3 4 1 3 6 : 36092
aida03 : 52 31 28 16 4 2 2 5 1 3 6 : 36744
aida04 : 6 8 20 12 4 4 3 4 2 2 6 : 35096
aida05 : 30 31 22 10 2 2 2 2 1 4 6 : 36752
aida06 : 12 6 10 5 2 3 3 2 2 3 6 : 35488
aida07 : 53 24 21 9 4 3 1 3 2 3 6 : 36228
aida08 : 36 28 28 9 0 2 3 3 3 2 6 : 35408
aida09 : 27 28 25 10 3 4 2 3 1 3 6 : 35548
aida10 : 50 23 26 7 3 1 1 3 3 3 6 : 36928
aida11 : 42 28 22 10 3 3 2 2 2 3 6 : 35944
aida12 : 39 35 15 10 2 2 2 4 3 2 6 : 35684
aida13 : 43 34 17 7 4 2 3 4 3 2 6 : 36012
aida14 : 42 32 16 10 3 4 3 4 3 2 6 : 36264
aida15 : 36 30 25 12 3 2 4 3 3 2 6 : 35920
aida16 : 40 21 25 15 3 4 2 3 1 3 6 : 35704
Collecting the file size of each FEE64 Options CONTENTS file to check they are all the same
FEE : aida01 => Options file size is 1026 Last changed Thu May 13 05:49:42 CEST 2021
FEE : aida02 => Options file size is 1014 Last changed Thu Apr 29 14:43:46 CEST 2021
FEE : aida03 => Options file size is 1014 Last changed Thu Apr 29 14:43:50 CEST 2021
FEE : aida04 => Options file size is 1025 Last changed Fri May 14 16:54:56 CEST 2021
FEE : aida05 => Options file size is 1014 Last changed Thu Apr 29 14:43:55 CEST 2021
FEE : aida06 => Options file size is 1014 Last changed Thu Apr 29 14:43:59 CEST 2021
FEE : aida07 => Options file size is 1014 Last changed Thu Apr 29 14:44:02 CEST 2021
FEE : aida08 => Options file size is 1025 Last changed Wed May 05 12:15:54 CEST 2021
FEE : aida09 => Options file size is 1014 Last changed Thu Apr 29 14:44:08 CEST 2021
FEE : aida10 => Options file size is 1014 Last changed Thu Apr 29 14:44:57 CEST 2021
FEE : aida11 => Options file size is 1014 Last changed Thu Apr 29 14:44:57 CEST 2021
FEE : aida12 => Options file size is 1014 Last changed Thu Apr 29 14:44:57 CEST 2021
FEE : aida13 => Options file size is 1025 Last changed Fri May 07 19:40:34 CEST 2021
FEE : aida14 => Options file size is 1014 Last changed Thu Apr 29 14:44:57 CEST 2021
FEE : aida15 => Options file size is 1014 Last changed Thu Apr 29 14:44:57 CEST 2021
FEE : aida16 => Options file size is 1014 Last changed Thu Apr 29 14:44:57 CEST 2021
19:40 Analysed R5_86. Attached. Dead time as before.
19:57 Shift handed over to James S |
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316
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Fri May 14 07:05:08 2021 |
CA | Friday 14th May 08:00 - 16:00 shift | 08:00 CA takes over
08:28 Problem at UNILAC - no beam
09:30 all system wide checks ok *except*
all FEE64 fail ADC calibration (no waveforms)
WR decoder status:
Base Current Difference
aida01 fault 0xf932 : 0xf933 : 1
aida02 fault 0x62ec : 0x62ed : 1
aida03 fault 0x8679 : 0x867a : 1
aida04 fault 0xf0e4 : 0xf0e5 : 1
aida05 fault 0x9db8 : 0x9dc2 : 10
aida06 fault 0x7f18 : 0x7f19 : 1
aida07 fault 0xdd2c : 0xdd2d : 1
aida08 fault 0x1557 : 0x1558 : 1
White Rabbit error counter test result: Passed 8, Failed 8
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
FPGA timestamp errors:
Base Current Difference
aida05 fault 0x0 : 0x2 : 2
FPGA Timestamp error counter test result: Passed 15, Failed 1
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
09:36 FEE64 Temperatures ok - attachment 1
Detector bias / leakage currents ok - attachment 2
Statistics - attachments 3-8
09:50 beam is back - writing to file R4_265
09:56 FRS adjusting degrader settings (S4) - temporarily remove to check counts in scintillator vs AIDA
10:10 FRS increase degrader thickness
10.28 all histograms, stats and merger stats zero'd
10.50 all system wide checks ok *except*
Base Current Difference
aida01 fault 0xf932 : 0xf933 : 1
aida02 fault 0x62ec : 0x62ed : 1
aida03 fault 0x8679 : 0x867a : 1
aida04 fault 0xf0e4 : 0xf0e5 : 1
aida05 fault 0x9db8 : 0x9dc2 : 10
aida06 fault 0x7f18 : 0x7f19 : 1
aida07 fault 0xdd2c : 0xdd2d : 1
aida08 fault 0x1557 : 0x1558 : 1
White Rabbit error counter test result: Passed 8, Failed 8
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
Base Current Difference
aida05 fault 0x0 : 0x3 : 3
FPGA Timestamp error counter test result: Passed 15, Failed 1
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
Returned 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 3 2 2 2 2 2 2 4 3 3 6 : 36860
aida02 : 7 3 5 1 2 5 2 4 3 3 6 : 37284
aida03 : 7 5 3 1 4 4 2 3 3 3 6 : 36756
aida04 : 3 1 20 4 2 3 3 5 1 3 6 : 36052
aida05 : 19 25 26 6 2 2 3 2 2 3 6 : 35828
aida06 : 1 3 16 1 3 4 1 5 1 3 6 : 35580
aida07 : 6 4 1 2 3 3 2 3 3 3 6 : 36552
aida08 : 8 5 2 3 2 3 2 2 2 4 6 : 37064
aida09 : 9 7 1 2 2 4 2 3 3 3 6 : 36652
aida10 : 2 5 3 1 1 4 2 3 3 3 6 : 36544
aida11 : 16 4 4 2 1 2 2 3 3 3 6 : 36384
aida12 : 2 1 1 3 1 2 2 3 3 3 6 : 36288
aida13 : 0 1 1 2 0 4 3 2 3 3 6 : 36184
aida14 : 6 3 2 0 2 3 2 3 3 3 6 : 36432
aida15 : 25 8 2 1 2 3 1 2 2 4 6 : 36836
aida16 : 3 5 1 2 2 2 3 2 3 3 6 : 36100
Collecting the file size of each FEE64 Options CONTENTS file to check they are all the same
FEE : aida01 => Options file size is 1026 Last changed Thu May 13 05:49:42 CEST 2021
FEE : aida02 => Options file size is 1014 Last changed Thu Apr 29 14:43:46 CEST 2021
FEE : aida03 => Options file size is 1014 Last changed Thu Apr 29 14:43:50 CEST 2021
FEE : aida04 => Options file size is 1014 Last changed Thu Apr 29 14:43:53 CEST 2021
FEE : aida05 => Options file size is 1014 Last changed Thu Apr 29 14:43:55 CEST 2021
FEE : aida06 => Options file size is 1014 Last changed Thu Apr 29 14:43:59 CEST 2021
FEE : aida07 => Options file size is 1014 Last changed Thu Apr 29 14:44:02 CEST 2021
FEE : aida08 => Options file size is 1025 Last changed Wed May 05 12:15:54 CEST 2021
FEE : aida09 => Options file size is 1014 Last changed Thu Apr 29 14:44:08 CEST 2021
FEE : aida10 => Options file size is 1014 Last changed Thu Apr 29 14:44:57 CEST 2021
FEE : aida11 => Options file size is 1014 Last changed Thu Apr 29 14:44:57 CEST 2021
FEE : aida12 => Options file size is 1014 Last changed Thu Apr 29 14:44:57 CEST 2021
FEE : aida13 => Options file size is 1025 Last changed Fri May 07 19:40:34 CEST 2021
FEE : aida14 => Options file size is 1014 Last changed Thu Apr 29 14:44:57 CEST 2021
FEE : aida15 => Options file size is 1014 Last changed Thu Apr 29 14:44:57 CEST 2021
FEE : aida16 => Options file size is 1014 Last changed Thu Apr 29 14:44:57 CEST 2021
10.50 DAQ continues S496/R4_304
11:18 FEE64 Temperatures ok - attachment 9
Detector bias & leakage currents ok - attachment 10
statistics - attachments 11-16
15:00 FEE64 avg. CPU usage (%)
1 52
2 55
3 55
4 60
5 93
6 50
7 53
8 55
9 55
10 51
11 50
12 67
13 56
14 55
15 55
16 58
15:08 all system wide checks ok *except*
all FEE64 fail ADC calibration (no waveform)
WR decoder status:
Base Current Difference
aida01 fault 0xf932 : 0xf933 : 1
aida02 fault 0x62ec : 0x62ed : 1
aida03 fault 0x8679 : 0x867a : 1
aida04 fault 0xf0e4 : 0xf0e5 : 1
aida05 fault 0x9db8 : 0x9dc3 : 11
aida06 fault 0x7f18 : 0x7f19 : 1
aida07 fault 0xdd2c : 0xdd2d : 1
aida08 fault 0x1557 : 0x1558 : 1
White Rabbit error counter test result: Passed 8, Failed 8
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
FPGA errors:
Base Current Difference
aida05 fault 0x0 : 0x3 : 3
FPGA Timestamp error counter test result: Passed 15, Failed 1
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
15:10 Temperatures ok - attachment 17
Detector bias / leakage current ok - attachment 18
Statistics - attachments 18 -24 |
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