AIDA GELINA BRIKEN nToF CRIB ISOLDE CIRCE nTOFCapture DESPEC DTAS EDI_PSA 179Ta CARME StellarModelling DCF K40
  DESPEC, Page 7 of 36  ELOG logo
New entries since:Thu Jan 1 01:00:00 1970
Entry  Sun Apr 3 10:56:11 2022, TD, Sunday 3 April 35x
all system wide checks OK *except* aida10 failed ADC calibration

Attachment 1 ADC data item stats
Attachment 2 FEE64 temps OK
Attachment 3 DSSSD bias & leakage currents OK





DSSSD bias to left (looking upstream) wafer *only*
      FEE64s 10 & 12, 14 & 16

Attachments 4 & 5 1.8.W spectra 20us FSR

Attachment 6 ADC data item stats

Attachment 7 DSSSD bias & leakage current




ASIC check all FEE64s

DSSSD bias to middle (looking upstream) wafer *only*
      FEE64s 1 & 3, 5 & 7

Attachments 8 & 9 1.8.W spectra 20us FSR

Attachment 10 ADC data item stats

Attachment 11 DSSSD bias & leakage current





ASIC check all FEE64s

DSSSD bias to right (looking upstream) wafer *only*
      FEE64s 9 & 11, 13 & 15

Attachments 12 & 13 1.8.W spectra 20us FSR

Attachment 14 ADC data item stats

Attachment 15 DSSSD bias & leakage current



Conclusions

ADC data item stats -> 300-400k

n+n 1.8.W spectra show large signal excursions

p+n 1.8.W spectra for biased Si wafers OK - unbiased Si wafers show large signal excursions


DSSSD#1 leakage currents 1.850+2.220+1.990=6.06uA    cf. 5.095uA with all 3 wafers biased 
DSSSD#2 leakage currents 1.510+1.580+2.350=5.44uA    cf. 5.235uA 


Right wafer (looking upstream)
             
Bias(V)         -20    -40    -60    -80    -100
DSSSD#1 I_L(uA) -1.135 -1.475 -1.645 -1.750 -1.805
DSSSD#2 I_l(uA) -1.625 -2.020 -2.205 -2.320 -2.360

Middle wafer (looking upstream)
          
Bias(V)         -20    -40    -60    -80    -100
DSSSD#1 I_L(uA) -1.540 -1.870 -2.035 -2.150 -2.210
DSSSD#2 I_l(uA) -0.985 -1.285 -1.465 -1.575 -1.615

Left wafer (looking upstream)
          
Bias(V)         -20    -40    -60    -80    -100
DSSSD#1 I_L(uA) -0.735 -0.915 -1.005 -1.080 -1.110
DSSSD#2 I_l(uA) -0.865 -1.205 -1.400 -1.510 -1.560

Bias versus leakage cuurent characteristic of each wafer of each DSSSD indicates diode behaviour.

Note LK1 not fitted - presumably LK3 of mid/top p+n FEE64 adaptor PCBs (aida01 and aida05) connecting n+n bias to gnd is sufficient to establish circuit.




15.50 Re-connect bias to all 3x Si wafers p+n junction side bias rings

ASIC check all FEE64s

Attachments 16 & 17 1.8.W spectra 20us FSR

Attachment 18 ADC data item stats

Attachment 19 DSSSD bias & leakage current

Conclusion - status quo ante restored



16.40 Remove aida01 & aida05 LK3, add aida04 & aida08 LK1

ASIC check all FEE64s

Attachments 20 & 21 1.8.W spectra 20us FSR

Attachment 22 ADC data item stats

Attachment 23 DSSSD bias & leakage current

Conclusion - no change



17.00 Add Thorn-Lab HV filters DSSSD#1 & #2


ASIC check all FEE64s

Attachments 24 & 25 1.8.W spectra 20us FSR

Attachment 26 ADC data item stats

Attachment 27 DSSSD bias & leakage current

Conclusion - aida09-aida12 no change, aida13-aida16 -> 300-400k
             I do not know why there's a difference between DSSSD#1 & #2 but more important point (probably) no improvement aida09-aida12
             Thorn Lab HV filters removed - status quo ante restored


18.02 Remove LK2 & LK4 all top p+n adaptor PCBs (aida13, 5, 14, 9, 1, & 10)

ASIC check all FEE64s

Attachments 28 & 29 1.8.W spectra 20us FSR

Attachment 30 ADC data item stats

Attachment 31 DSSSD bias & leakage current

Conclusion - no change cf. 16.40 test



19.10 Re-order power cabling at AIDA FEE64 PSUs from ...

Top    1-3 2-4 9-10 11-12
Bottom 5-7 6-8 13-14 15-16

to ...

Top    1-2 3-4 9-10 11-12
Bottom 5-6 7-8 13-14 15-16


ASIC check all FEE64s

Attachments 32 & 33 1.8.W spectra 20us FSR

Attachment 34 ADC data item stats

Attachment 35 DSSSD bias & leakage current

Conclusion - all p+n FEE64 rates c. 100k, or less, n+n FEE64 rates c. 400k

FEE64 adaptor PCB config

LK2-LK3-LK4 fitted for all bottom p+n FEE64s (aida11, 3, 12, 15, 7, 16)

LK1 fitted n+n FEE64s aida06 & aida02 *only*
Entry  Mon Apr 4 09:19:49 2022, TD, Monday 4 April 12x
AIDA adaptor PCB config - all LKs removed *except*

aida04 & aida08 LK1

aida02 & aida07 LK2, LK3 & LK4

aida09, aida01, aida10, aida11, aida15, aida12 & aida16 LK2 & LK4



10.05 check all ASICs all FEE64s
      zero histograms

Attachment 1 per FEE64 rate spectra

Attachment 2 per FEE64 p+n 1.8.L spectra - aida10 peak width 79 ch FWHM

Attachment 3 per FEE64 p+n 1.8.W spectra 20us FSR

Attachment 4 per FEE64 n+n 1.8.W spectra 20us FSR

Attachments 5-8 - system wide checks - all OK *except*

  FPGA timestamp errors no longer works
  aida05 & aida09 report WR decoder error 0x10

Attachment 9 ADC data item stats

Attachment 10 FEE64 temps OK

Attachment 11 DSSSD bias & leakage current OK

Attachment 12 per FEE64 n+n 1.8.L spectra - aida08 peak width 369 ch FWHM


14.25 DAQ STOP
      DSSSD bias OFF

      AIDA triple snout removed from AIDA stand and moved to table by aida-gsi (Messeheute)
Entry  Tue Apr 5 08:52:16 2022, TD, Tuesday 5 April 6x
DSSSD bias OFF. DAQ STOPped

Attachment 1 FEE64 temps OK

Attachment 2 system wide checks OK *except* WR decoder (attachment 2) and FPGA ts errors no longer works

Attachment 6 System wide check - 'Synchronise ASIC clocks'

Attachment 5 System wide check - check ADC calibration - all 16x FEE64s fail

Attachment 4 System wide check - WR decoder status - aida09 WR status 0x10 clears

Repeat Synchronsie ASIC clocks

Attachment 3 System wide check - WR decoder status - aida05 WR status 0x10 clears
             
Entry  Tue Apr 5 12:46:52 2022, TD, MSL type BB18(DS)-1000 triple - cable lengths 
OH/NH disassembling current AIDA triple snout and DSSSD stack.

Length of ribbon cables (including connector) outside snout as follows

p+n junction side 9cm & 15cm
n+n ohmic side 10.5cm & 16cm 


Update
p+n junction side: 6.5cm, 10.5 cm (used  7.5, 11.5 for 1cm slack)
n+n ohmic side:  11.0 cm, 15.0 cm (used 12.0, 16.0 for 1cm slack)
Measurement from SAMTEC connector to exit from the rubber seals in AIDA snout.
Entry  Sat May 7 09:55:53 2022, TD, Saturday 7 May 15x
Attachments 1 & 2 per FEE64 1.8.L spectra 
 pulser peak widths aida01 121 ch FWHM, aida02 517 ch FWHM

Attachments 3 & 4 per FEE64 1.8.W spectra 20us FSR

Attachment 5 per FEE64 rate spectra

Attachment 6 - grafana DSSSD bias/leakage current for previous 7 days showing effect of day/night temp variations

Attachments 7 & 8 - merger & tape server c. 14Mb/s to disk - no errors reported by servers

Attachments 9-12 - system wide checks - all OK

Attachment 13 ADC data item stats

Attachment 14 FEE64 temps OK

Attachment 15 DSSSD bias & leakage currents OK

16.15 aida05 zero ADC data items stats
      merger restart, DAQ STOP/Go cycle to recover


      activity is S4 area near AIDA DSSSDs as install of DEGAS detectors commences

19.50 DEGAS install continues

      DSSSD bias and FEE64 power OFF
 
Entry  Sat May 7 13:27:39 2022, TD, AIDA configuration 
Adaptor PCB link settings

n+n FEE64s

aida02, 4, 6 & 8 - LK1 fitted, HV Lemo-00 not connected - left/right wafer n+n side bias ring -> gnd

p+n FEE64s

   top - aida09, 1, 10 & aida13, 5, 14 - LK2 & LK4 fitted - front/back FP -> gnd
bottom - aida11, 3, 12 & aida15, 7, 16 - LK2 & LK4 fitted - front/back FP -> gnd

   top - aida01, 5 - LK3 fitted - middle wafer n+n side bias ring -> gnd
bottom - aida03, 7 - LK3 fitted - DSSSD PCB gnd -> gnd

AIDA PSU

   top 1-2, 3-4, 9-10, 11-12
bottom 5-6, 7-8, 13-14, 15-16


ASIC settings 2021Apr29-13-16-00
     slow comparator 0x64 -> 0xa

BNC PB-5 settings
    amplitude 1.000V
    attenuation x1
    tail pulse
    tau_d 1ms
    polarity +
    frequency 25Hz
Entry  Sun May 8 15:10:45 2022, TD, Sunday 8 May 6x
DSSSD bias and FEE64 power OFF during Ge install



Photographs of AIDA (triple) + DEGAS setup as of Sunday pm.

Attachments 1-4 side/front/oblique views - note AIDA snout droops and twists

Attachments 5 & 6 - position of the AIDA stand vertical adjustment threads (brass) 

The asymmetry upstream-downstream pre-dates this setup. To lift the end of the snout clear of the of lower DEGAS detectors all 3x 1/4 turns clockwise (viewed from above) were applied to each of the four threads.
Entry  Thu May 12 07:09:43 2022, TD, Thursday 12 May 08:00-24:00 27x
08.10 AIDA DAQ status
    
      14x FEE64s configured - aida05, aida14 power OFF - dhcpd.conf changed - aida15 -> aida05, aida16 -> aida14
2
      AD9222 OFF - waveforms disabed
      disc - all disabled

      ASIC settings 2021Apr29-13-16-00
       slow comparator 0xc *except* aida02 & aida04 0x16, aida06 & aida08 0x23

      BNC PB-5
      amplitude 1.000V
      attenuation x1
      tau_d 1ms (tail pulse)
      polarity +
      frequency 22Hz

08.14 all histograms zero'd
2
08.15 system wide check counter baseline

08.17 check ASIC control - all FEE64s all ASICs

Attachment 1 - grafana DSSSD bias & leakage current - OK

Attachment 2 - per FEE64 stat spectra

Attachments 3 & 4 - per FEE64 1.8.H spectra - few events c. 5GeV p+n strips

Attachments 5 & 6 - per FEE64 1.8.L spectra
 pulser peak width aida01 124ch FWHM, aida04 293ch FWHM

Attachment 7 - per FEE64 rate spectra

Attachments 8-12 - system wide checks - all OK

Attachments 13-16 - statistics - adc, pause, resume & correlation data

Attachment 17 - FEE64 temps OK

Attachment 18 - DSSSD bias & leakage current OK - start new section of googledoc spreadsheet to monitor long term trends

Attachments 19 & 20 - NewMerger & TapeServer - OK - no warning messages

08.44 DAQ continues - file NOTAPE/R18 - no storage mode

08.47 switch to storage mode to generate data file to evaluate FEE64 dead times etc

08.53 no storage mode enabled

Attachment 21 - analysis of file NOTAPE/R18_20

Attachment 22- analysis of file NOTAPE/R19_19
               AIDA12 slow comp up to 0xd improved deadtime drastically for FEE

10:54 Beam on detector. Take another run to test deadtime - attachment 23
      Deadtimes ranging from 10-40% in n+n FEEs

Attachment 23 & 24 aida06 aida02 1.*.H spectra


14:07 - Currently no beam so had acces. OH checked the cables on AIDA12 were seated correctly. No improvement in the rate for 12 but better for remaining p+n strips.
        Tested running with dataspy off for PCS but observed no change in the deadtimes (Other than a decrease because no beamtime)
Entry  Sat May 14 23:02:33 2022, TD, Sunday 15 May 00:00-08:00 48x
Pb beam c. 1e+9/spill

00.02 zero all histograms
      system wide checks - baseline counters

00.08 ASIC check control - all FEE64s, all ASICs

Attachment 1 - grafana DSSSD bias, leakage current & temp - OK

Attachments 2 & 3 - ucesb - AIDA DSSSD #1 c. 10-20Hz peak rate on spill, c. 0Hz off spill

Attachment 4 - DSSSD bias & Leakage current - OK

Attachment 5 - FEE64 temps OK

Attachment 6-13 - adc, pause, resume & correlation scaler data items, push, flush, aida01, aida06

Attachments 14-18 - system wide checks - all OK *except* aida09 clock fail status 6

Attachments 19-25 - iptraf, TapeServer, NewMerger, NewMerger stats



00.44 file S450/R4_792

      ADC control register 0xff

      all disc outputs disabled

      ASIC settings 2021Apr29-13-16-00
       slow comparator aida02 & aida04 0x16, aida06 & aida08 0x23, aida12 0xd, all others 0xc

      BNC PB-5 settings
      amplitude 1.000V
      attenuation x1
      tau_d 1ms
      frequency 2Hz
      polarity +

00.51 disk space OK - c. 3' per data file

[npg@aidas-gsi S450]$ ls -l /
total 40
lrwxrwxrwx.   1 root root     7 Oct 18  2021 bin -> usr/bin
dr-xr-xr-x.   5 root root  4096 May 12 18:31 boot
drwxr-xr-x.  23 root root  4100 May 12 18:31 dev
drwxr-xr-x. 145 root root  8192 May 12 18:31 etc
drwxr-xr-x.   4 root root    56 Jan 28 14:56 home
lrwxrwxrwx.   1 root root     7 Oct 18  2021 lib -> usr/lib
lrwxrwxrwx.   1 root root     9 Oct 18  2021 lib64 -> usr/lib64
drwxr-xr-x.   5 root root   113 Apr 28 11:58 media
lrwxrwxrwx.   1 root root    45 Oct 18  2021 MIDAS -> /home/npg/MIDAS_Releases/23Jan19/MIDAS_200119
drwxr-xr-x.   2 root root     6 Apr 11  2018 mnt
drwxr-xr-x.   3 root root    16 Oct 18  2021 opt
dr-xr-xr-x. 464 root root     0 May 12 18:30 proc
dr-xr-x---.  10 root root  4096 May 13 11:47 root
drwxr-xr-x.  44 root root  1360 May 14 06:34 run
lrwxrwxrwx.   1 root root     8 Oct 18  2021 sbin -> usr/sbin
drwxr-xr-x.   2 root root     6 Apr 11  2018 srv
dr-xr-xr-x.  13 root root     0 May 12 18:31 sys
lrwxrwxrwx.   1 root root    28 Apr 28 14:19 TapeData -> /media/SecondDrive/TapeData/
drwxrwxrwt.  40 root root 12288 May 15 00:49 tmp
drwxr-xr-x.  13 root root   155 Oct 18  2021 usr
drwxr-xr-x.  21 root root  4096 Oct 18  2021 var
[npg@aidas-gsi S450]$ df -h
Filesystem               Size  Used Avail Use% Mounted on
devtmpfs                 7.8G     0  7.8G   0% /dev
tmpfs                    7.8G  373M  7.4G   5% /dev/shm
tmpfs                    7.8G   19M  7.7G   1% /run
tmpfs                    7.8G     0  7.8G   0% /sys/fs/cgroup
/dev/mapper/centos-root   50G   16G   35G  31% /
/dev/sda2               1014M  226M  789M  23% /boot
/dev/sda1                200M   12M  189M   6% /boot/efi
/dev/sde1                7.2T  3.1T  3.8T  46% /media/SecondDrive
/dev/mapper/centos-home  407G   91G  316G  23% /home
tmpfs                    1.6G   52K  1.6G   1% /run/user/1000
/dev/sdd1                7.2T  6.5T  310G  96% /run/media/npg/ThirdDrive

Attachment 26 - analysis data file R4_792

Attachments 27-28 - per FEE64 rate & stat spectra - shows distro HEC events

Attachments 29-30 - per FEE64 1.8.L spectra 
 pulser peak widths aida01 134 ch FWHM, aida04 393 ch FWHM

Attachments 31-32 - per FEE64 1.8.H spectra

Attachments 33-34 - aida02 & aida04 1.*.H spectra

04.13

Attachment 35 - DSSSD bias & Leakage current - OK

Attachment 36 - FEE64 temps OK

Attachment 37 - adc data item stats

Attachments 38 - ucesb

system wide checks - all OK *except* aida09 clock fail status 6


07.05

Attachment 39 - DSSSD bias & Leakage current - OK

Attachment 40 - FEE64 temps OK

Attachment 41 - adc data item stats

Attachments 42 - ucesb

system wide checks - all OK *except* aida09 clock fail status 6

Attachments 43-48 - aida02 & aida04 & aida06 & aida08 & 1.*.H spectra
Entry  Mon May 16 14:07:06 2022, TD, Lost activity monitor Screenshot_from_2022-05-16_15-04-56.png
 
Entry  Mon May 16 17:23:27 2022, TD, NewMerger stats Screenshot_from_2022-05-16_18-17-10.pngScreenshot_from_2022-05-16_18-17-50.pngScreenshot_from_2022-05-16_18-18-24.pngScreenshot_from_2022-05-16_18-20-02.png
 
Entry  Tue May 17 16:53:20 2022, TD, Tuesday 17 May 16.00-00.00 24x
17.35 zero all histograms
      zero statistics
      zero NewMerger statistics

      ASIC check control - all FEE64s, all ASICs

      file no storage mode, no MBS data transfer

      ADC control register 0xff

      all disc outputs disabled

      ASIC settings 2021Apr29-13-16-00
       slow comparator 0x80

      BNC PB-5 settings
      amplitude 1.000V
      attenuation x1
      tau_d 1ms
      frequency 2Hz
      polarity +

Attachment 1 - grafana DSSSD bias, leakage current & temp - OK

Attachments 2-10 - NewMerger stats

Attachments 11-13 - iptraf, TapeServer, NewMerger

Attachment 14 - per Fee64 rate spectra

Attachment 15 - lost activity  monitor

Attachment 16 - ASIC settings aida01

Attachments 17-22 - adc, pause, resume & correlation scaler data items, push, flush, aida01 & aida06 stats

Attachment 23 - FEE64 temperatures OK

Attachment 24 - DSSSD bias & leakage current
Entry  Wed May 18 15:29:50 2022, TD, Wednesday 18 May 8x
      file no storage mode, no MBS data transfer

      ADC control register 0x0 

      std disc outputs disabled

      ASIC settings 2021Apr29-13-16-00
       slow comparator 0xa

      BNC PB-5 settings
      amplitude 1.000V
      attenuation x1
      tau_d 1ms
      frequency 2Hz
      polarity +

Attachment 1 - DSSSD bias & leakage current

Attachment 2 - grafana DSSSD bias, leakage current & temp - OK

Attachment 3 - ADC data item stats

Attachment 4 - FEE64 temps - OK

16.35 zero all histograms
      zero statistics
      zero NewMerger statistics

      ASIC check control - all FEE64s, all ASICs

      baseline counters
      system wide checks - all OK *except* aida07 WR error 0x10

Attachment 5 - per FEE64 rate spectra

Attachmnents 6 & 7 - per FEE64 1.8.W spectra 20us FSR
Entry  Thu May 19 17:00:46 2022, TD, Thursday 19 May  Screenshot_from_2022-05-19_17-59-41.pngScreenshot_from_2022-05-19_17-58-21.pngScreenshot_from_2022-05-19_17-58-52.pngScreenshot_from_2022-05-19_17-59-20.png
18.01 DAQ stopped

Attachment 1 - grafana DSSSD bias, leakage current & temp - OK

Attachment 2 - DSSSD bias & leakage current

Attachment 3 - FEE64 temps - OK

Attachment 4 - ADC data item stats
Entry  Fri May 20 16:22:01 2022, TD, Friday 20 May Screenshot_from_2022-05-20_17-19-21.pngScreenshot_from_2022-05-20_17-19-35.pngScreenshot_from_2022-05-20_17-20-22.png
17.20 DAQ stopped

Attachment 1 - DSSSD bias & leakage current

Attachment 2 - grafana DSSSD bias, leakage current & temp - OK

Attachment 3 - FEE64 temps - OK
Entry  Sat May 21 15:30:45 2022, TD, Saturday 21 May Screenshot_from_2022-05-21_16-27-58.pngScreenshot_from_2022-05-21_16-28-59.pngScreenshot_from_2022-05-21_16-29-36.png
16.31 DAQ stopped

Attachment 1 - DSSSD bias & leakage current

Attachment 2 - grafana DSSSD bias, leakage current - OK, temp data has ceased

Attachment 3 - FEE64 temps - OK
Entry  Sun May 22 14:12:55 2022, TD, Sunday 22 May Screenshot_from_2022-05-22_15-10-25.pngScreenshot_from_2022-05-22_15-10-48.pngScreenshot_from_2022-05-22_15-11-35.png
15.11 DAQ stopped

Attachment 1 - DSSSD bias & leakage current

Attachment 2 - grafana DSSSD bias, leakage current - OK, temp data has ceased

Attachment 3 - FEE64 temps - OK
Entry  Mon May 23 16:41:45 2022, TD, Monday 23 May Screenshot_from_2022-05-23_17-39-23.pngScreenshot_from_2022-05-23_17-39-58.pngScreenshot_from_2022-05-23_17-40-33.png
17.40 DAQ stopped

Attachment 1 - DSSSD bias & leakage current

Attachment 2 - grafana DSSSD bias, leakage current - OK, temp data has ceased

Attachment 3 - FEE64 temps - OK
Entry  Tue May 31 17:09:35 2022, TD, Tuesday 31 May 20x
2x MSL type BB18(DS)-1000 installed


Adaptor PCB LK config

all FEE64s LK2, LK4 fitted
n+n FEE64s LK1 fitted
bottom p+n FEE64s LK3 fitted


AIDA PSU config

top 1-3 2-4
bottom 5-7 6-8


DSSSD bias -> p+n FEE64 core, n+n FEE64 braid


Heavy duty grounds not connected to FEE64 adaptor PCBs


ASIC settings 2021Apr29-13-16-00
 slow comparator 0xa

BNC PB-5 settings
 amplitude 1.000V
 attenuation x1
 tau_d 1ms
 frequency 25Hz
 polarity +


Attachment 1 - DSSSD bias & Leakage current - OK

Attachment 2 - FEE64 temps OK

Attachment 3 - adc data item stats

Attachments 4-9 - system wide checks OK *except* aida07 fails ADC calibration

Attachments 10 & 11 - 1.8.W spectra 20us FSR

Attachments 12 & 13 - 1.8.L spectra - aida03 pulser peak width 155 ch FWHM

Attachment 14 - per FEE64 rate spectra



19.15 Attachments 15-18 - 2*W spectra for aida01, 02, 03 &04

Attachment 19 - per FEE64 rate spectra

Attachment 20 - adc data item stats
Entry  Wed Jun 1 07:35:13 2022, TD, Wednesday 1 June 15x
Attachment 1 - DSSSD bias & leakage current - OK

Attachment 2 - ADC data item stats

Attachment 3 - FEE64 temps - OK

Attachments 4-7 - aida01, 02, 03 & 04 2.*.W spectra

Noise observed for asics #1 & #2 of aida02 consistent with no cable attached - confirmed by visual inspection - ribbon cable disconnected from Samtec header of adaptor PCB

To Do list

1) re-connect ribbon cable to aida02 adaptor PCB
2) good quality ground to snout - use screws at inter-stage
3) install heavy duty grounds
4) ... 


Attachment 8 - adc data item stats - slow comparator 0x64

Attachment 9 - per FEE64 rate spectra - slow comparator 0x64

Attachment 10 - per FEE64 rate spectra - slow comparator 0xa

-

13:30 - Attach heavy duty ground to AIDA 

Attachment 11 - per FEE64 rate spectra - slow comparator 0xa

Try power cycle as system ground changed significantly now

Try to reattach aida04 TTY connector - still wrong

Archive old tty logs (ttyUSB*) to zip and delete them, makes easier to track startup 

Attachment 12 - per FEE64 rate spectra - slow comparator 0xa

No major difference, aida01 quieter than before

aida05 has some missing channels - loose ERNI?

Attachements 13 & 14 - Waveforms

Temporarily raise to 0x64 and test merger for DTAS synchro test later... all works good to MBS 
Change NETVAR MERGE.LinksAvailable to 8

Notice one copper screw touching aluminium, add some kapton tape behind it to isolate it. No difference

Voltage diff between aida02,aida06 < 1 mV
Voltage diff between copper bars < 0.5 mV (but not 0)

A comment from DTAS people that they observed a large increase in noise recently - perhaps from accelerator
May indicate current power/gronud oddities?

Attachment 15 - Rates at 0x1f (= 310 keV)

DSSSD#1 reasonable (aida04 a bit bad), but mostly just pulser (25 Hz)

DSSSD#2 much worse esp. p+n sides (aida05, aida07)

ERNI connectors pushed in and feel fully in
ELOG V3.1.4-unknown