 Tue Apr 2 12:36:25 2024, JB, CC, NH, Installing FEE64s of DSSSD2 cont.
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Some additional checks
- check 'top hat' electrical isolators are correctly installed at each of the 4x mounting points of the AIDA snout
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Wed Mar 27 14:22:35 2024, JB, NH, Installing FEE64s of DSSSD2 14x
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Mounted on frame:
DSSD 1 (Upstream) : 3208-2/3208-5/3208-8
DSSD 2 (Downstream): 3208-3/3208-21/3208-22 |
 Thu Mar 28 09:18:53 2024, TD, Installing FEE64s of DSSSD2
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Some additional checks
- check 'top hat' electrical isolators are correctly installed at each of the 4x mounting points of the AIDA snout assembly
- check snout is electrically isolated with respect to AIDA support assembly/stand, bPlas PCBs/cabling/ground/drain wires and BB7 |
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Tue Mar 26 18:56:03 2024, TD, USB-controlled ac mains relay interlock box - wiring
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Sensor ( 4 pins )
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Tue Mar 26 10:32:05 2024, NH, JB, Tue 26 March 9x
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Taken 4 FEE64s from CRYRING (the 4 easiest to access)
41:d8:2b
41:f6:5a
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Fri Mar 22 08:31:39 2024, TD, Friday 22 March 39x
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09.30 Systems check
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Fri Mar 22 08:29:55 2024, TD, Anydesk restarted remotely
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Anydesk restarted remotely per https://elog.ph.ed.ac.uk/CARME/489
Anydesk address now restored to 832827869 |
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Thu Mar 21 15:41:49 2024, NH, AM, MP, CC, Thu Mar 21 6x
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Fig 1-3: Noise situation at real thresholds (0xa p+n, 0xf n+n)
Fig 4-6: After AM and MP turn off Mesytec Preamps
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Fri Mar 22 08:22:43 2024, NH, AM, MP, CC, Thu Mar 21
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> Fig 1-3: Noise situation at real thresholds (0xa p+n, 0xf n+n)
>
> Fig 4-6: After AM and MP turn off Mesytec Preamps
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Fri Mar 22 07:34:54 2024, NH, JB, Au Beam
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Wed Mar 20 17:02:53 2024, NH, /dev/sdd
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The following messages are in the system log very often:
Mar 20 18:00:56 aidas-gsi smartd[1076]: Device: /dev/sdd [SAT], 2224 Currently unreadable (pending) sectors
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Wed Mar 20 12:22:27 2024, NH, Wed Mar 20 9x
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Turn on AIDA for Dry Run demonstrations and so on
All system wide checks, temp, bias OK
Noise situation is dreadful (but has not been optimised). Deterioriation since first mounted, suspect cabling issues with bPlast and BB7. |
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Tue Mar 19 10:17:30 2024, NH, Dry Run 2024 - 19th March 24
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AIDA has 8 FEEs and 1 DSSSD
Aida08 (HDMI#12) had no WR again, I moved it to a different MACB and now it gets WR
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Mon Mar 18 18:04:43 2024, NH, Preparation for pre-s100 dry run (and test beam???)
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In preparation for the dry run the following *temporary* changes to the FEE numbering have been prepared
These should be reverted after the dry run to ensure cable->fee agreement again
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Fri Mar 15 16:29:57 2024, NH, Leakage currents
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The behaviour of the DSSSD leakage current at low voltages and during biases is unusual and varies depending on how the adapter boards are connected
To summarise the behaviour I have observed
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Thu Mar 14 13:00:23 2024, JB, NH, MA, AM, GA, Mounting and biasing DSSD 2
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new Downstream DSSD2: 3208-2/3208-5/3208-8
Covered with black cloth. |
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Thu Mar 14 12:13:17 2024, JB, NH, MA, Mounting and biasing DSSD 1
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Upstream bPlast mounted
new Upstream DSSD: 3208-2/3208-5/3208-8
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Wed Mar 13 13:02:19 2024, JB, NH, HA, MA, DSSD 1 biasing tests
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Dismounted Snout and biased DSSSD1 channels
leftmost waifer working
middle waifer reaches 90V then current ramps up |
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Tue Mar 12 16:16:49 2024, NH, TD, JB, HA, Summary of DSSSD Biasing 12.03
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DSSD#1 undergoes a breakdown at 90V, two of the three wafers show this
- The adapter PCBs themselves have no breakdown at 100V, indicating the issue is internal to the snout
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Mon Mar 11 15:19:44 2024, JB, NH, Priyanka, Michael Armstrong, Helena Albers, To Do: AIDA PCB tests
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To do:
1) Disconnect ribbon cables from p+n junction FEE64 adaptor PCBs of upstream DSSSD, apply c. 100V bias and check leakage current is zero
i.e. eliminate shorts in PCBs |
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Sun Mar 10 17:08:12 2024, NH, AIDA FEE Layout + Cabling Plan for S100
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Proposed FEE numbering and wiring plan for upcoming experiment S100 (2x Wide DSSSDs)
Image designed in draw.io, source attached
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Fri Mar 8 16:05:57 2024, JB, CC, TD, NH, Friday 8 March
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Bias tests of AIDA on individual wafers and in parallel. Spreadsheet can be found in attachment 1, and graphic results can be seen in Attachment 2. Summary:
Upstream detector cannot be biased in parallel nor individually. Downstream detector can be biased with positively and each wafer can individually be biased
negatively. In parallel, it was not possible to bias the downstream detector negatively as indicated by the tests below. |